Unaligned instruction relocation

Bertolli, Carlo; O'Brien, John K.; Sallenave, Olivier H.; Sura, Zehra N.

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Title: Unaligned instruction relocation

Abstract

In one embodiment, a computer-implemented method includes receiving source code to be compiled into an executable file for an unaligned instruction set architecture (ISA). Aligned assembled code is generated, by a computer processor. The aligned assembled code complies with an aligned ISA and includes aligned processor code for a processor and aligned accelerator code for an accelerator. A first linking pass is performed on the aligned assembled code, including relocating a first relocation target in the aligned accelerator code that refers to a first object outside the aligned accelerator code. Unaligned assembled code is generated in accordance with the unaligned ISA and includes unaligned accelerator code for the accelerator and unaligned processor code for the processor. A second linking pass is performed on the unaligned assembled code, including relocating a second relocation target outside the unaligned accelerator code that refers to an object in the unaligned accelerator code.

Inventors:: Bertolli, Carlo; O'Brien, John K.; Sallenave, Olivier H.; Sura, Zehra N.

Issue Date:: Tue Jan 23 00:00:00 EST 2018

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1417876

Patent Number(s):: 9875089

Application Number:: 14/744,047

Assignee:: INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F8/445 - {Exploiting fine grain parallelism, i.e. parallelism at instruction level
G06F8/54 - Link editing before load time
G06F9/3001 - {Arithmetic instructions}
G06F9/3012 - {Organisation of register space, e.g. banked or distributed register file}

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DOE Contract Number:: B599858

Resource Type:: Patent

Resource Relation:: Patent File Date: 2015 Jun 19

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Bertolli, Carlo, O'Brien, John K., Sallenave, Olivier H., and Sura, Zehra N. Unaligned instruction relocation.  United States: N. p., 2018. 
        Web.

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                    Bertolli, Carlo, O'Brien, John K., Sallenave, Olivier H., & Sura, Zehra N. Unaligned instruction relocation.  United States.

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                    Bertolli, Carlo, O'Brien, John K., Sallenave, Olivier H., and Sura, Zehra N. Tue .  
        "Unaligned instruction relocation".  United States.  https://www.osti.gov/servlets/purl/1417876.

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@article{osti_1417876,

  title        = {Unaligned instruction relocation},

  author       = {Bertolli, Carlo and O'Brien, John K. and Sallenave, Olivier H. and Sura, Zehra N.},

  abstractNote = {In one embodiment, a computer-implemented method includes receiving source code to be compiled into an executable file for an unaligned instruction set architecture (ISA). Aligned assembled code is generated, by a computer processor. The aligned assembled code complies with an aligned ISA and includes aligned processor code for a processor and aligned accelerator code for an accelerator. A first linking pass is performed on the aligned assembled code, including relocating a first relocation target in the aligned accelerator code that refers to a first object outside the aligned accelerator code. Unaligned assembled code is generated in accordance with the unaligned ISA and includes unaligned accelerator code for the accelerator and unaligned processor code for the processor. A second linking pass is performed on the unaligned assembled code, including relocating a second relocation target outside the unaligned accelerator code that refers to an object in the unaligned accelerator code.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {Tue Jan 23 00:00:00 EST 2018},

  month        = {Tue Jan 23 00:00:00 EST 2018}

}

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Works referenced in this record:

Relocatable file format and method and apparatus for creating and loading same
patent, June 1998

Eidt, Erik L.; Lillich, Alan W.
US Patent Document 5,764,987
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5764987

Instruction compression and decompression system and method for a processor
patent, October 1998

Miller, Richard G.; Cardillo, Louis A.; Mathieson, John George
US Patent Document 5,819,058
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5819058

Assembler system and method for a geometry accelerator
patent, March 1999

Strunk, Glenn W.
US Patent Document 5,889,997
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5889997

Object-code compatible representation of very long instruction word programs
patent, September 1999

Moreno, Jaime
US Patent Document 5,951,674
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5951674

Linker using relocation sequences
patent, October 2004

Shann, Richard
US Patent Document 6,802,060
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6802060

Aligning load/store data with big/little endian determined rotation distance control
patent, November 2004

Shepherd, David
US Patent Document 6,820,195
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6820195

Method and software for multithreaded processor with partitioned operations
patent, September 2008

Hansen, Craig; Moussouris, John
US Patent Document 7,430,655
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7430655

Conflict-free register allocation
patent, September 2014

Patney, Anjul; Dally, William J.
US Patent Document 8,832,671
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8832671

Transforming non-contiguous instruction specifiers to contiguous instruction specifiers
patent, March 2016

Gschwind, Michael K.
US Patent Document 9,280,347
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9280347

Instruction to load data up to a specified memory boundary indicated by the instruction
patent, July 2016

Bradbury, Jonathan D.; Gschwind, Michael K.; Jacobi, Christian
US Patent Document 9,383,996
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9383996

Rewriting symbol address initialization sequences
patent, July 2016

Gschwind, Michael K.; Weigand, Ulrich
US Patent Document 9,384,130
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9384130

Method, apparatus and article for generation of debugging information
patent-application, July 2003

Bowers, Antony; Shann, Richard
US Patent Document 10/206381; 20030140338
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20030140338

System and software for matched aligned and unaligned storage instructions
patent-application, August 2004

Hansen, Craig; Moussouris, John
US Patent Document 10/716568; 20040158689
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20040158689

Multiple-thread processor for threaded software applications
patent-application, January 2005

Tremblay, Marc; Joy, William
US Patent Document 10/818785; 20050010743
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20050010743

System and method for simulating hardware interrupts
patent-application, July 2006

Erb, David John
US Patent Document 11/002533; 20060149943
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20060149943

Programming environment for heterogeneous processor resource integration
patent-application, October 2008

Wang, Perry; Collins, Jamison; Chinya, Gautham
US Patent Document 11/786920; 20080256330
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20080256330

Methods and Apparatus for Storage and Translation of Entropy Encoded Software Embedded within a Memory Hierarchy
patent-application, November 2012

Larin, Sergei; Codrescu, Lucian; Das Gupta, Anshuman
US Patent Application 13/099463; 20120284461
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20120284461

Efficient Enqueuing of Values in SIMD Engines with Permute Unit
patent-application, June 2013

Eichenberger, Alexandre E.; O'Brien, John K. P.; Zhao, Yuan
US Patent Document 13/315596; 20130151822
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20130151822

Processors, Methods, Systems, and Instructions to Generate Sequences of Integers in which Integers in Consecutive Positions Differ by a Constant Integer Stride and Where a Smallest Integer is Offset from Zero by an Integer Offset
patent-application, October 2013

Abraham, Seth; Ould-Ahmed-Vall, Elmoustapha; Valentine, Robert
US Patent Document 13/976580; 20130275727
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20130275727

Address calculation for retargetable compilation and exploration of instruction-set architectures
conference, January 1996

Liem, C.; Paulin, P.; Jerrava, A.
33rd Design Automation Conference Proceedings, 1996
https://doi.org/10.1109/DAC.1996.545645

Implementation and evaluation of the Complex Streamed Instruction set
conference, January 2001

Juurlink, B.; Tcheressiz, D.; Vassiliadis, S.
Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques
https://doi.org/10.1109/PACT.2001.953289

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Similar Records

Title: Unaligned instruction relocation

Abstract

Citation Formats

Relocatable file format and method and apparatus for creating and loading same patent, June 1998

Instruction compression and decompression system and method for a processor patent, October 1998

Assembler system and method for a geometry accelerator patent, March 1999

Object-code compatible representation of very long instruction word programs patent, September 1999

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Aligning load/store data with big/little endian determined rotation distance control patent, November 2004

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Instruction to load data up to a specified memory boundary indicated by the instruction patent, July 2016

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System and software for matched aligned and unaligned storage instructions patent-application, August 2004

Multiple-thread processor for threaded software applications patent-application, January 2005

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Programming environment for heterogeneous processor resource integration patent-application, October 2008

Methods and Apparatus for Storage and Translation of Entropy Encoded Software Embedded within a Memory Hierarchy patent-application, November 2012

Efficient Enqueuing of Values in SIMD Engines with Permute Unit patent-application, June 2013

Processors, Methods, Systems, and Instructions to Generate Sequences of Integers in which Integers in Consecutive Positions Differ by a Constant Integer Stride and Where a Smallest Integer is Offset from Zero by an Integer Offset patent-application, October 2013

Address calculation for retargetable compilation and exploration of instruction-set architectures conference, January 1996

Implementation and evaluation of the Complex Streamed Instruction set conference, January 2001

Relocatable file format and method and apparatus for creating and loading same
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Instruction compression and decompression system and method for a processor
patent, October 1998

Assembler system and method for a geometry accelerator
patent, March 1999

Object-code compatible representation of very long instruction word programs
patent, September 1999

Linker using relocation sequences
patent, October 2004

Aligning load/store data with big/little endian determined rotation distance control
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Method and software for multithreaded processor with partitioned operations
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Transforming non-contiguous instruction specifiers to contiguous instruction specifiers
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Instruction to load data up to a specified memory boundary indicated by the instruction
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Rewriting symbol address initialization sequences
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Method, apparatus and article for generation of debugging information
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System and software for matched aligned and unaligned storage instructions
patent-application, August 2004

Multiple-thread processor for threaded software applications
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System and method for simulating hardware interrupts
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Programming environment for heterogeneous processor resource integration
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Methods and Apparatus for Storage and Translation of Entropy Encoded Software Embedded within a Memory Hierarchy
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Efficient Enqueuing of Values in SIMD Engines with Permute Unit
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Processors, Methods, Systems, and Instructions to Generate Sequences of Integers in which Integers in Consecutive Positions Differ by a Constant Integer Stride and Where a Smallest Integer is Offset from Zero by an Integer Offset
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