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Title: Unaligned instruction relocation

Patent ·
OSTI ID:1525022

In one embodiment, a computer-implemented method includes receiving source code to be compiled into an executable file for an unaligned instruction set architecture (ISA). Aligned assembled code is generated, by a computer processor. The aligned assembled code complies with an aligned ISA and includes aligned processor code for a processor and aligned accelerator code for an accelerator. A first linking pass is performed on the aligned assembled code, including relocating a first relocation target in the aligned accelerator code that refers to a first object outside the aligned accelerator code. Unaligned assembled code is generated in accordance with the unaligned ISA and includes unaligned accelerator code for the accelerator and unaligned processor code for the processor. A second linking pass is performed on the unaligned assembled code, including relocating a second relocation target outside the unaligned accelerator code that refers to an object in the unaligned accelerator code.

Research Organization:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
B599858
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Number(s):
10,223,091
Application Number:
15/654,991
OSTI ID:
1525022
Resource Relation:
Patent File Date: 2017-07-20
Country of Publication:
United States
Language:
English

References (10)

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Software development for a hybrid computing environment patent September 2014
Data processing apparatus with instruction encodings to enable near and far memory access modes patent May 2017
Method, apparatus and article for generation of debugging information patent-application July 2003
Multiple-thread processor for threaded software applications patent-application January 2005

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