Unaligned instruction relocation
Patent
·
OSTI ID:1399904
In one embodiment, a computer-implemented method includes receiving source code to be compiled into an executable file for an unaligned instruction set architecture (ISA). Aligned assembled code is generated, by a computer processor. The aligned assembled code complies with an aligned ISA and includes aligned processor code for a processor and aligned accelerator code for an accelerator. A first linking pass is performed on the aligned assembled code, including relocating a first relocation target in the aligned accelerator code that refers to a first object outside the aligned accelerator code. Unaligned assembled code is generated in accordance with the unaligned ISA and includes unaligned accelerator code for the accelerator and unaligned processor code for the processor. A second linking pass is performed on the unaligned assembled code, including relocating a second relocation target outside the unaligned accelerator code that refers to an object in the unaligned accelerator code.
- Research Organization:
- International Business Machines Corporation, Armonk, NY (United States)
- Sponsoring Organization:
- USDOE
- Assignee:
- INTERNATIONAL BUSINESS MACHINES CORPORATION
- Patent Number(s):
- 9,792,098
- Application Number:
- 14/667,933
- OSTI ID:
- 1399904
- Country of Publication:
- United States
- Language:
- English
| DMA++: on the fly data realignment for on-chip memories | conference | January 2010 |
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