Global to push GA events into
skip to main content

Title: Unaligned instruction relocation

In one embodiment, a computer-implemented method includes receiving source code to be compiled into an executable file for an unaligned instruction set architecture (ISA). Aligned assembled code is generated, by a computer processor. The aligned assembled code complies with an aligned ISA and includes aligned processor code for a processor and aligned accelerator code for an accelerator. A first linking pass is performed on the aligned assembled code, including relocating a first relocation target in the aligned accelerator code that refers to a first object outside the aligned accelerator code. Unaligned assembled code is generated in accordance with the unaligned ISA and includes unaligned accelerator code for the accelerator and unaligned processor code for the processor. A second linking pass is performed on the unaligned assembled code, including relocating a second relocation target outside the unaligned accelerator code that refers to an object in the unaligned accelerator code.
Inventors:
; ; ;
Issue Date:
OSTI Identifier:
1399904
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION OSTI
Patent Number(s):
9,792,098
Application Number:
14/667,933
Contract Number:
B599858
Resource Relation:
Patent File Date: 2015 Mar 25
Research Org:
International Business Machines Corporation, Armonk, NY (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Other works cited in this record:

Method of relocating file and system therefor
patent, October 1994

Relocatable file format and method and apparatus for creating and loading same
patent, June 1998

Instruction compression and decompression system and method for a processor
patent, October 1998

Assembler system and method for a geometry accelerator
patent, March 1999

Object-code compatible representation of very long instruction word programs
patent, September 1999

System and method using extended relocation types and operations in relocating operations
patent, June 2003

Linker using relocation sequences
patent, October 2004

Aligning load/store data with big/little endian determined rotation distance control
patent, November 2004

Relocation format for linking
patent, November 2007

System and software for matched aligned and unaligned storage instructions
patent, June 2008

Method and software for multithreaded processor with partitioned operations
patent, September 2008

Instructions for efficiently accessing unaligned partial vectors
patent, November 2009

System and method for blurring instructions and data via binary obfuscation
patent, December 2013

Method and system for optimizing an executable program by generating special operations for identical program entities
patent, April 2014

Program executable image encryption
patent, June 2014

ISA bridging including support for call to overidding virtual functions
patent, July 2014

Conflict-free register allocation
patent, September 2014

Systems and methods for watermarking software and other media
patent, November 2014

Transforming non-contiguous instruction specifiers to contiguous instruction specifiers
patent, March 2016

Instruction to load data up to a specified memory boundary indicated by the instruction
patent, July 2016

Rewriting symbol address initialization sequences
patent, July 2016

Method, apparatus and article for generation of debugging information
patent-application, July 2003

System and software for matched aligned and unaligned storage instructions
patent-application, August 2004

Multiple-thread processor for threaded software applications
patent-application, January 2005

System and method for simulating hardware interrupts
patent-application, July 2006

Efficient Streaming of Un-Aligned Load/Store Instructions that Save Unused Non-Aligned Data in a Scratch Register for the Next Instruction
patent-application, May 2007

Programming environment for heterogeneous processor resource integration
patent-application, October 2008

Methods and Apparatus for Storage and Translation of Entropy Encoded Software Embedded within a Memory Hierarchy
patent-application, November 2012

Efficient Enqueuing of Values in SIMD Engines with Permute Unit
patent-application, June 2013

Processors, Methods, Systems, and Instructions to Generate Sequences of Integers in which Integers in Consecutive Positions Differ by a Constant Integer Stride and Where a Smallest Integer is Offset from Zero by an Integer Offset
patent-application, October 2013

Binary Translator Driven Program State Relocation
patent-application, August 2014

DMA++: on the fly data realignment for on-chip memories
conference, January 2010

Similar records in DOepatents and OSTI.GOV collections: