Generating and executing programs for a floating point single instruction multiple data instruction set architecture
Abstract
Mechanisms for generating and executing programs for a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA) are provided. A computer program product comprising a computer recordable medium having a computer readable program recorded thereon is provided. The computer readable program, when executed on a computing device, causes the computing device to receive one or more instructions and execute the one or more instructions using logic in an execution unit of the computing device. The logic implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA), based on data stored in a vector register file of the computing device. The vector register file is configured to store both scalar and floating point values as vectors having a plurality of vector elements.
- Inventors:
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1083443
- Patent Number(s):
- 8423983
- Application Number:
- 12/250,581
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- B554331
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Gschwind, Michael K. Generating and executing programs for a floating point single instruction multiple data instruction set architecture. United States: N. p., 2013.
Web.
Gschwind, Michael K. Generating and executing programs for a floating point single instruction multiple data instruction set architecture. United States.
Gschwind, Michael K. Tue .
"Generating and executing programs for a floating point single instruction multiple data instruction set architecture". United States. https://www.osti.gov/servlets/purl/1083443.
@article{osti_1083443,
title = {Generating and executing programs for a floating point single instruction multiple data instruction set architecture},
author = {Gschwind, Michael K},
abstractNote = {Mechanisms for generating and executing programs for a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA) are provided. A computer program product comprising a computer recordable medium having a computer readable program recorded thereon is provided. The computer readable program, when executed on a computing device, causes the computing device to receive one or more instructions and execute the one or more instructions using logic in an execution unit of the computing device. The logic implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA), based on data stored in a vector register file of the computing device. The vector register file is configured to store both scalar and floating point values as vectors having a plurality of vector elements.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Apr 16 00:00:00 EDT 2013},
month = {Tue Apr 16 00:00:00 EDT 2013}
}
Save to My Library
You must Sign In or Create an Account in order to save documents to your library.
Works referenced in this record:
Dependency analysis system and method
patent, August 2009
- Song, Yonghong; Kong, Xiangyun
- US Patent Document 7,581,215
Optimized Scalar Promotion with Load and Splat SIMD Instructions
patent-application, December 2009
- Eichenberger, Alexandre E.; GSchwind, Michael K.; Gunnels, JOhn A.
- US Patent Application 12/134495; 20090307656
Denormalization system and method of operation
patent, July 1997
- Taborn, Michael P.; Burchfiel, Steven Michael; Matheny, David Terrence
- US Patent Document 5,646,875
SIMD Vectorization of Straight Line FFT Code
book, January 2003
- Kral, Stefan; Franchetti, Franz; Lorenz, Juergen
- Euro-Par 2003 Parallel Processing
Methods for performing extended table lookups using SIMD vector permutation instructions that support out-of-range index values
patent, June 2011
- Moyer, William C.
- US Patent Document 7,962,718
Compiler with cache utilization optimizations
patent, July 2010
- Archambault, Roch G.; Blainey, Robert J.; Gao, Yaoqing
- US Patent Document 7,765,534
Map compiler pipelined loop structure
patent, November 2006
- Hammes, Jeffrey
- US Patent Document 7,134,120
An Open Source Environment for Cell Broadband Engine System Software
journal, June 2007
- Gschwind, Michael; Erb, David; Manning, Sid
- Computer, Vol. 40, Issue 6
Using advanced compiler technology to exploit the performance of the Cell Broadband Engine™ architecture
journal, January 2006
- Eichenberger, A. E.; O'Brien, J. K.; O'Brien, K. M.
- IBM Systems Journal, Vol. 45, Issue 1
Chip multiprocessing and the cell broadband engine
conference, January 2006
- Gschwind, Michael
- Proceedings of the 3rd conference on Computing frontiers - CF '06
Complex Matrix Multiplication Operations with Data Pre-Conditioning in a High Performance Computing Architecture
patent-application, February 2011
- Eichenberger, Alexandre E.; Gschwind, Michael K.; Gunnels, John A.
- US Patent Application 12/542324; 20110040822
Method for compiling scalar code for a single instruction multiple data (SIMD) execution engine
patent, August 2011
- Gschwind, Michael K.
- US Patent Document 8,010,953
Alignment and ordering of vector elements for single instruction multiple data processing
patent, August 1999
- Van Hook, Timothy J.; Hsu, Peter; Huffman, William A.
- US Patent Document 5,933,650
IBM PowerPC 440 FPU with complex-arithmetic extensions
journal, March 2005
- Wait, C. D.
- IBM Journal of Research and Development, Vol. 49, Issue 2.3
Sharing compiler optimizations in a multi-node system
patent, February 2012
- Barsness, Eric L.; Darrington, David L.; Peters, Amanda
- US Patent Document 8,122,441
A high-performance SIMD floating point unit for BlueGene/L: architecture, compilation, and algorithm design
conference, January 2004
- Bachega, L.; Chatterjee, S.; Dockser, K. A.
- Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004.
Dual function system and method for shuffling packed data elements
patent, March 2000
- Roussel, Patrice; Chennupaty, Srinivas; Cranford, Mike
- US Patent Document 6,041,404
Automatic Intra-Register Vectorization for the Intel® Architecture
journal, January 2002
- Bik, Aart J. C.; Girkar, Milind; Grey, Paul M.
- International Journal of Parallel Programming, Vol. 30, Issue 2, p. 65-98
Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations
patent, March 2011
- Gschwind, Michael K.
- US Patent Document 7,900,025
Vectorization for SIMD architectures with alignment constraints
conference, January 2004
- Eichenberger, Alexandre E.; Wu, Peng; O'Brien, Kevin
- Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation - PLDI '04
Efficient function interpolation using SIMD vector permute functionality
patent, August 2005
- Fossum, Gordon Clyde; Hofstee, Harm Peter; Minor, Barry L.
- US Patent Document 6,924,802
Insertion of Operation-and-Indicate Instructions for Optimized SIMD Code
patent-application, February 2011
- Eichenberger, Alexandre E.; Gara, Alan; Gschwind, MIchael K.
- US Patent Application 12/543628; 20110047359
Aligning precision converted vector data using mask indicating offset relative to element boundary corresponding to precision type
patent, January 2011
- Eichenberger, Alexandre E.; Fleischer, Bruce M.; Gschwind, Michael K.
- US Patent Document 7,865,693
Compiler analysis for cache coherence: interprocedural array data-flow analysis and its impact on cache performance
journal, January 2000
- Choi, L.; Yew, Pen-Chung
- IEEE Transactions on Parallel and Distributed Systems, Vol. 11, Issue 9, p. 879-896
The Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a Chip Multiprocessor
journal, April 2007
- Gschwind, Michael
- International Journal of Parallel Programming, Vol. 35, Issue 3
Synergistic Processing in Cell's Multicore Architecture
journal, March 2006
- Gschwind, M.; Hofstee, H. P.; Flachs, B.
- IEEE Micro, Vol. 26, Issue 2
An integrated simdization framework using virtual vectors
conference, January 2005
- Wu, Peng; Eichenberger, Alexandre E.; Wang, Amy
- Proceedings of the 19th annual international conference on Supercomputing - ICS '05
Compilation for a SIMD RISC processor
patent, November 2010
- Gschwind, Michael K.
- US Patent Document 7,840,954
Optimizing Compiler for the CELL Processor
conference, January 2005
- Eichenberger, A. E.; O'Brien, K.; O'Brien, K.
- PACT 2005. 14th International Conference on Parallel Architectures and Compilation Techniques, 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05)
Method and apparatus for performing integer operations in response to a result of a floating point operation
patent, November 2001
- Thakkar, Shreekant S.; Scott, Wayne; Roussel, Patrice
- US Patent Document 6,317,824
Using a shuffle unit to implement shift operations in a processor
patent, December 2008
- Tan, Teik-Chung; Goveas, Kelvin D.
- US Patent Document 7,464,255
Logical inference techniques for loop parallelization
journal, August 2012
- Oancea, Cosmin E.; Rauchwerger, Lawrence
- ACM SIGPLAN Notices, Vol. 47, Issue 6
SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode
patent, January 2005
- Gschwind, Michael K.; Hofstee, Harm Peter; Hopkins, Martin E.
- US Patent Document 6,839,828
Method for optimizing array bounds checks in programs
patent, January 2002
- Gupta, Manish; Midkiff, Samuel; Moreira, Jose E.
- US Patent Document 6,343,375