Generating and executing programs for a floating point single instruction multiple data instruction set architecture

Gschwind, Michael K

Title: Generating and executing programs for a floating point single instruction multiple data instruction set architecture

Patent · Tue Apr 16 00:00:00 EDT 2013

OSTI ID:1083443

Gschwind, Michael K

Mechanisms for generating and executing programs for a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA) are provided. A computer program product comprising a computer recordable medium having a computer readable program recorded thereon is provided. The computer readable program, when executed on a computing device, causes the computing device to receive one or more instructions and execute the one or more instructions using logic in an execution unit of the computing device. The logic implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA), based on data stored in a vector register file of the computing device. The vector register file is configured to store both scalar and floating point values as vectors having a plurality of vector elements.

View Patent

Cite

Export

Save

Research Organization:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Organization:: USDOE

DOE Contract Number:: B554331

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Number(s):: 8,423,983

Application Number:: 12/250,581

OSTI ID:: 1083443

Country of Publication:: United States

Language:: English

References (36)

Dependency analysis system and method Song, Yonghong; Kong, Xiangyun https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7581215 US Patent Document 7,581,215	patent	August 2009
Optimized Scalar Promotion with Load and Splat SIMD Instructions Eichenberger, Alexandre E.; GSchwind, Michael K.; Gunnels, JOhn A. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090307656 US Patent Application 12/134495; 20090307656	patent-application	December 2009
Denormalization system and method of operation Taborn, Michael P.; Burchfiel, Steven Michael; Matheny, David Terrence https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5646875 US Patent Document 5,646,875	patent	July 1997
Vectorized table lookup Sazegari, Ali https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6446198 US Patent Document 6,446,198	patent	September 2002
DFG Program Oldfield, Frank PAGES news, Vol. 7, Issue 3 https://doi.org/10.22498/pages.7.3.15a	journal	December 1999
SIMD Vectorization of Straight Line FFT Code Kral, Stefan; Franchetti, Franz; Lorenz, Juergen Euro-Par 2003 Parallel Processing https://doi.org/10.1007/978-3-540-45209-6_39	book	January 2003
Methods for performing extended table lookups using SIMD vector permutation instructions that support out-of-range index values Moyer, William C. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7962718 US Patent Document 7,962,718	patent	June 2011
Compiler with cache utilization optimizations Archambault, Roch G.; Blainey, Robert J.; Gao, Yaoqing https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7765534 US Patent Document 7,765,534	patent	July 2010
Map compiler pipelined loop structure Hammes, Jeffrey https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7134120 US Patent Document 7,134,120	patent	November 2006
An Open Source Environment for Cell Broadband Engine System Software Gschwind, Michael; Erb, David; Manning, Sid Computer, Vol. 40, Issue 6 https://doi.org/10.1109/MC.2007.192	journal	June 2007
Using advanced compiler technology to exploit the performance of the Cell Broadband Engine™ architecture Eichenberger, A. E.; O'Brien, J. K.; O'Brien, K. M. IBM Systems Journal, Vol. 45, Issue 1 https://doi.org/10.1147/sj.451.0059	journal	January 2006
Chip multiprocessing and the cell broadband engine Gschwind, Michael Proceedings of the 3rd conference on Computing frontiers - CF '06 https://doi.org/10.1145/1128022.1128023	conference	January 2006
Complex Matrix Multiplication Operations with Data Pre-Conditioning in a High Performance Computing Architecture Eichenberger, Alexandre E.; Gschwind, Michael K.; Gunnels, John A. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20110040822 US Patent Application 12/542324; 20110040822	patent-application	February 2011
Method for compiling scalar code for a single instruction multiple data (SIMD) execution engine Gschwind, Michael K. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8010953 US Patent Document 8,010,953	patent	August 2011
Alignment and ordering of vector elements for single instruction multiple data processing Van Hook, Timothy J.; Hsu, Peter; Huffman, William A. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5933650 US Patent Document 5,933,650	patent	August 1999
IBM PowerPC 440 FPU with complex-arithmetic extensions Wait, C. D. IBM Journal of Research and Development, Vol. 49, Issue 2.3 https://doi.org/10.1147/rd.492.0249	journal	March 2005
Sharing compiler optimizations in a multi-node system Barsness, Eric L.; Darrington, David L.; Peters, Amanda https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8122441 US Patent Document 8,122,441	patent	February 2012
A high-performance SIMD floating point unit for BlueGene/L: architecture, compilation, and algorithm design Bachega, L.; Chatterjee, S.; Dockser, K. A. Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004. https://doi.org/10.1109/PACT.2004.1342544	conference	January 2004
Dual function system and method for shuffling packed data elements Roussel, Patrice; Chennupaty, Srinivas; Cranford, Mike https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6041404 US Patent Document 6,041,404	patent	March 2000
Automatic Intra-Register Vectorization for the Intel® Architecture Bik, Aart J. C.; Girkar, Milind; Grey, Paul M. International Journal of Parallel Programming, Vol. 30, Issue 2, p. 65-98 https://doi.org/10.1023/A:1014230429447	journal	January 2002
Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations Gschwind, Michael K. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7900025 US Patent Document 7,900,025	patent	March 2011
Vectorization for SIMD architectures with alignment constraints Eichenberger, Alexandre E.; Wu, Peng; O'Brien, Kevin Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation - PLDI '04 https://doi.org/10.1145/996841.996853	conference	January 2004
Efficient function interpolation using SIMD vector permute functionality Fossum, Gordon Clyde; Hofstee, Harm Peter; Minor, Barry L. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6924802 US Patent Document 6,924,802	patent	August 2005
Insertion of Operation-and-Indicate Instructions for Optimized SIMD Code Eichenberger, Alexandre E.; Gara, Alan; Gschwind, MIchael K. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20110047359 US Patent Application 12/543628; 20110047359	patent-application	February 2011
Aligning precision converted vector data using mask indicating offset relative to element boundary corresponding to precision type Eichenberger, Alexandre E.; Fleischer, Bruce M.; Gschwind, Michael K. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7865693 US Patent Document 7,865,693	patent	January 2011
Compiler analysis for cache coherence: interprocedural array data-flow analysis and its impact on cache performance Choi, L.; Yew, Pen-Chung IEEE Transactions on Parallel and Distributed Systems, Vol. 11, Issue 9, p. 879-896 https://doi.org/10.1109/71.879772	journal	January 2000
The Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a Chip Multiprocessor Gschwind, Michael International Journal of Parallel Programming, Vol. 35, Issue 3 https://doi.org/10.1007/s10766-007-0035-4	journal	April 2007
Synergistic Processing in Cell's Multicore Architecture Gschwind, M.; Hofstee, H. P.; Flachs, B. IEEE Micro, Vol. 26, Issue 2 https://doi.org/10.1109/MM.2006.41	journal	March 2006
An integrated simdization framework using virtual vectors Wu, Peng; Eichenberger, Alexandre E.; Wang, Amy Proceedings of the 19th annual international conference on Supercomputing - ICS '05 https://doi.org/10.1145/1088149.1088172	conference	January 2005
Compilation for a SIMD RISC processor Gschwind, Michael K. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7840954 US Patent Document 7,840,954	patent	November 2010
Optimizing Compiler for the CELL Processor Eichenberger, A. E.; O'Brien, K.; O'Brien, K. PACT 2005. 14th International Conference on Parallel Architectures and Compilation Techniques, 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05) https://doi.org/10.1109/PACT.2005.33	conference	January 2005
Method and apparatus for performing integer operations in response to a result of a floating point operation Thakkar, Shreekant S.; Scott, Wayne; Roussel, Patrice https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6317824 US Patent Document 6,317,824	patent	November 2001
Using a shuffle unit to implement shift operations in a processor Tan, Teik-Chung; Goveas, Kelvin D. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7464255 US Patent Document 7,464,255	patent	December 2008
Logical inference techniques for loop parallelization Oancea, Cosmin E.; Rauchwerger, Lawrence ACM SIGPLAN Notices, Vol. 47, Issue 6 https://doi.org/10.1145/2345156.2254124	journal	August 2012
SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode Gschwind, Michael K.; Hofstee, Harm Peter; Hopkins, Martin E. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6839828 US Patent Document 6,839,828	patent	January 2005
Method for optimizing array bounds checks in programs Gupta, Manish; Midkiff, Samuel; Moreira, Jose E. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6343375 US Patent Document 6,343,375	patent	January 2002

Similar Records

Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations

Patent · Tue Mar 01 00:00:00 EST 2011 · OSTI ID:1083443

Gschwind, Michael K

An efficient and portable SIMD algorithm for charge/current deposition in Particle-In-Cell codes

Journal Article · Mon Sep 19 00:00:00 EDT 2016 · Computer Physics Communications · OSTI ID:1083443

Vincenti, H.; Lobet, M.; Lehe, R.; +2 more

Index Sets and Vectorization

Conference · Tue Mar 27 00:00:00 EDT 2012 · OSTI ID:1083443

Keasler, J A

Related Subjects

97 MATHEMATICS AND COMPUTING

Title: Generating and executing programs for a floating point single instruction multiple data instruction set architecture

Citation Formats

References (36)

Similar Records

Related Subjects