Dynamic remapping of cache lines
Abstract
A method of managing cache memory includes accessing a cache memory at a primary index that corresponds to an address specified in an access request. A determination is made that accessing the cache memory at the primary index does not result in a cache hit on a cache line with an error-free status. In response to this determination, the primary index is mapped to a secondary index and data for the address is written to a cache line at the secondary index.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1531936
- Patent Number(s):
- 9424195
- Application Number:
- 14/253,785
- Assignee:
- Advanced Micro Devices, Inc. (Sunnyvale, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
- DOE Contract Number:
- AC52-07NA27344; B600716
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2014-04-15
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Kalamatianos, John, John, Johnsy Kanjirapallil, Nevius, Phillip E., and Gelinas, Robert G. Dynamic remapping of cache lines. United States: N. p., 2016.
Web.
Kalamatianos, John, John, Johnsy Kanjirapallil, Nevius, Phillip E., & Gelinas, Robert G. Dynamic remapping of cache lines. United States.
Kalamatianos, John, John, Johnsy Kanjirapallil, Nevius, Phillip E., and Gelinas, Robert G. Tue .
"Dynamic remapping of cache lines". United States. https://www.osti.gov/servlets/purl/1531936.
@article{osti_1531936,
title = {Dynamic remapping of cache lines},
author = {Kalamatianos, John and John, Johnsy Kanjirapallil and Nevius, Phillip E. and Gelinas, Robert G.},
abstractNote = {A method of managing cache memory includes accessing a cache memory at a primary index that corresponds to an address specified in an access request. A determination is made that accessing the cache memory at the primary index does not result in a cache hit on a cache line with an error-free status. In response to this determination, the primary index is mapped to a secondary index and data for the address is written to a cache line at the secondary index.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Aug 23 00:00:00 EDT 2016},
month = {Tue Aug 23 00:00:00 EDT 2016}
}
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