Dynamic memory remapping to reduce row-buffer conflicts

Eckert, Yasuko; Panda, Reena; Jayasena, Nuwan

Title: Dynamic memory remapping to reduce row-buffer conflicts

Abstract

A data processing system includes a memory that includes a first memory bank and a second memory bank. The data processing system also includes a conflict detector connected to the memory and adapted to receive memory access information. The conflict detector tracks memory access statistics of the first memory bank, and determines if the first memory bank contains frequent row conflicts. The conflict detector also remaps a frequent row conflict in the first memory bank to the second memory bank. An indirection table is connected to the conflict detector and adapted to receive a memory access request, and redirects an address into a dynamically selected physical memory address in response to a remapping of the frequent row conflict to the second memory bank.

Inventors:: Eckert, Yasuko; Panda, Reena; Jayasena, Nuwan

Issue Date:: 2019-02-05

Research Org.:: Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1531406

Patent Number(s):: 10198369

Application Number:: 15/469,071

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F2212/7206 - Reconfiguration of flash memory system
G06F13/4068 - {Electrical coupling}
G06F2212/7201 - Logical to physical mapping or translation of blocks or pages
G06F12/0246 - {in block erasable memory, e.g. flash memory}
G06F13/1642 - {with request queuing}
G06F13/1673 - {using buffers}

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
Y02D10/00 - Energy efficient computing

G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
G11C11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers

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DOE Contract Number:: AC52-07NA27344; B609201

Resource Type:: Patent

Resource Relation:: Patent File Date: 2017-03-24

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Eckert, Yasuko, Panda, Reena, and Jayasena, Nuwan. Dynamic memory remapping to reduce row-buffer conflicts.  United States: N. p., 2019. 
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                    Eckert, Yasuko, Panda, Reena, & Jayasena, Nuwan. Dynamic memory remapping to reduce row-buffer conflicts.  United States.

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                    Eckert, Yasuko, Panda, Reena, and Jayasena, Nuwan. Tue .  
        "Dynamic memory remapping to reduce row-buffer conflicts".  United States.  https://www.osti.gov/servlets/purl/1531406.

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@article{osti_1531406,

  title        = {Dynamic memory remapping to reduce row-buffer conflicts},

  author       = {Eckert, Yasuko and Panda, Reena and Jayasena, Nuwan},

  abstractNote = {A data processing system includes a memory that includes a first memory bank and a second memory bank. The data processing system also includes a conflict detector connected to the memory and adapted to receive memory access information. The conflict detector tracks memory access statistics of the first memory bank, and determines if the first memory bank contains frequent row conflicts. The conflict detector also remaps a frequent row conflict in the first memory bank to the second memory bank. An indirection table is connected to the conflict detector and adapted to receive a memory access request, and redirects an address into a dynamically selected physical memory address in response to a remapping of the frequent row conflict to the second memory bank.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2019},

  month        = {2}

}

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Works referenced in this record:

System and method for remapping defective memory locations
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Jeddeloh, Joseph M.
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Title: Dynamic memory remapping to reduce row-buffer conflicts

Abstract

Citation Formats

System and method for remapping defective memory locations patent, January 1999

Finding frequent items in data streams journal, January 2004

System, apparatus, and method for transparent page level instruction translation patent, May 2016

A simple algorithm for finding frequent elements in streams and bags journal, March 2003

Arbiter system for central processing unit having dual dominoed encoders for four instruction issue per machine cycle patent, June 2001

System and method for remapping defective memory locations
patent, January 1999

Finding frequent items in data streams
journal, January 2004

System, apparatus, and method for transparent page level instruction translation
patent, May 2016

A simple algorithm for finding frequent elements in streams and bags
journal, March 2003

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patent, June 2001