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Title: Compressing data for storage in cache memories in a hierarchy of cache memories

Abstract

An electronic device includes at least one compression-decompression functional block and a hierarchy of cache memories with a first cache memory and a second cache memory. The at least one compression-decompression functional block receives data in an uncompressed state, compresses the data using one of a first compression or a second compression, and, after compressing the data, provides the data to the first cache memory for storage therein. When the data is retrieved from the first cache memory to be stored in the second cache memory, when the data is compressed using the first compression, the compression-decompression functional block decompresses the data to reverse effects of the first compression on the data, thereby restoring the data to the uncompressed state and provides the data compressed using the second compression or in the uncompressed state to the second cache memory for storage therein.

Inventors:
; ;
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1771481
Patent Number(s):
10795825
Application Number:
16/232,314
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
AC52-07NA27344; B620717
Resource Type:
Patent
Resource Relation:
Patent File Date: 12/26/2018
Country of Publication:
United States
Language:
English

Citation Formats

Tomei, Matthew J., Bedoukian, Philip B., and Das, Shomit N. Compressing data for storage in cache memories in a hierarchy of cache memories. United States: N. p., 2020. Web.
Tomei, Matthew J., Bedoukian, Philip B., & Das, Shomit N. Compressing data for storage in cache memories in a hierarchy of cache memories. United States.
Tomei, Matthew J., Bedoukian, Philip B., and Das, Shomit N. Tue . "Compressing data for storage in cache memories in a hierarchy of cache memories". United States. https://www.osti.gov/servlets/purl/1771481.
@article{osti_1771481,
title = {Compressing data for storage in cache memories in a hierarchy of cache memories},
author = {Tomei, Matthew J. and Bedoukian, Philip B. and Das, Shomit N.},
abstractNote = {An electronic device includes at least one compression-decompression functional block and a hierarchy of cache memories with a first cache memory and a second cache memory. The at least one compression-decompression functional block receives data in an uncompressed state, compresses the data using one of a first compression or a second compression, and, after compressing the data, provides the data to the first cache memory for storage therein. When the data is retrieved from the first cache memory to be stored in the second cache memory, when the data is compressed using the first compression, the compression-decompression functional block decompresses the data to reverse effects of the first compression on the data, thereby restoring the data to the uncompressed state and provides the data compressed using the second compression or in the uncompressed state to the second cache memory for storage therein.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {10}
}

Works referenced in this record:

HyComp: a hybrid cache compression method for selection of data-type-specific compression methods
conference, December 2015

  • Arelakis, Angelos; Dahlgren, Fredrik; Stenstrom, Per
  • MICRO-48: The 48th Annual IEEE/ACM International Symposium of Microarchitecture, Proceedings of the 48th International Symposium on Microarchitecture
  • https://doi.org/10.1145/2830772.2830823

A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems
journal, May 2016