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Title: Dynamic cache bypassing

Abstract

A processing system fills a memory access request for data from a processor core by bypassing a cache when a write congestion condition is detected, and when transferring the data to the cache would cause eviction of a dirty cache line. The cache is bypassed by transferring the requested data to the processor core or to a different cache. Accordingly, the processing system can temporarily bypass the cache storing the dirty cache line when filling a memory access request, thereby avoiding the eviction and write back to main memory of a dirty cache line when a write congestion condition exists.

Inventors:
;
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1637804
Patent Number(s):
10599578
Application Number:
15/377,537
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
DOE Contract Number:  
AC52-07NA27344
Resource Type:
Patent
Resource Relation:
Patent File Date: 12/13/2016
Country of Publication:
United States
Language:
English

Citation Formats

Farmahini-Farahani, Amin, and Roberts, David A. Dynamic cache bypassing. United States: N. p., 2020. Web.
Farmahini-Farahani, Amin, & Roberts, David A. Dynamic cache bypassing. United States.
Farmahini-Farahani, Amin, and Roberts, David A. Tue . "Dynamic cache bypassing". United States. https://www.osti.gov/servlets/purl/1637804.
@article{osti_1637804,
title = {Dynamic cache bypassing},
author = {Farmahini-Farahani, Amin and Roberts, David A.},
abstractNote = {A processing system fills a memory access request for data from a processor core by bypassing a cache when a write congestion condition is detected, and when transferring the data to the cache would cause eviction of a dirty cache line. The cache is bypassed by transferring the requested data to the processor core or to a different cache. Accordingly, the processing system can temporarily bypass the cache storing the dirty cache line when filling a memory access request, thereby avoiding the eviction and write back to main memory of a dirty cache line when a write congestion condition exists.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {3}
}

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Works referenced in this record:

Open high speed bus for microcomputer system
patent, May 1996


Speculative cache line write backs to avoid hotspots
patent, September 2000


Data storage apparatus and methods
patent, December 2014


Reducing cache misses by snarfing writebacks in non-inclusive memory systems
patent, June 1999