Efficient accesses of data structures using processing near memory
Abstract
Systems, apparatuses, and methods for implementing efficient queues and other data structures. A queue may be shared among multiple processors and/or threads without using explicit software atomic instructions to coordinate access to the queue. System software may allocate an atomic queue and corresponding queue metadata in system memory and return, to the requesting thread, a handle referencing the queue metadata. Any number of threads may utilize the handle for accessing the atomic queue. The logic for ensuring the atomicity of accesses to the atomic queue may reside in a management unit in the memory controller coupled to the memory where the atomic queue is allocated.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1444107
- Patent Number(s):
- 9977609
- Application Number:
- 15/063,186
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC52-07NA27344
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2016 Mar 07
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Jayasena, Nuwan S., Zhang, Dong Ping, and Diez, Paula Aguilera. Efficient accesses of data structures using processing near memory. United States: N. p., 2018.
Web.
Jayasena, Nuwan S., Zhang, Dong Ping, & Diez, Paula Aguilera. Efficient accesses of data structures using processing near memory. United States.
Jayasena, Nuwan S., Zhang, Dong Ping, and Diez, Paula Aguilera. Tue .
"Efficient accesses of data structures using processing near memory". United States. https://www.osti.gov/servlets/purl/1444107.
@article{osti_1444107,
title = {Efficient accesses of data structures using processing near memory},
author = {Jayasena, Nuwan S. and Zhang, Dong Ping and Diez, Paula Aguilera},
abstractNote = {Systems, apparatuses, and methods for implementing efficient queues and other data structures. A queue may be shared among multiple processors and/or threads without using explicit software atomic instructions to coordinate access to the queue. System software may allocate an atomic queue and corresponding queue metadata in system memory and return, to the requesting thread, a handle referencing the queue metadata. Any number of threads may utilize the handle for accessing the atomic queue. The logic for ensuring the atomicity of accesses to the atomic queue may reside in a management unit in the memory controller coupled to the memory where the atomic queue is allocated.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue May 22 00:00:00 EDT 2018},
month = {Tue May 22 00:00:00 EDT 2018}
}
Save to My Library
You must Sign In or Create an Account in order to save documents to your library.
Works referenced in this record:
Priority differentiated subtree locking
patent-application, February 2004
- Szilagyi, Zoltan C.; Rhoten, Matthew Paul; Su, Phillip Ti-Fei
- US Patent Document 10/222953; 20040034642
Fine-grain task aggregation and coordination on GPUs
journal, October 2014
- Orr, Marc S.; Beckmann, Bradford M.; Reinhardt, Steven K.
- ACM SIGARCH Computer Architecture News, Vol. 42, Issue 3, p. 181-192
Data-Driven Versus Topology-driven Irregular Computations on GPUs
conference, May 2013
- Nasre, Rupesh; Burtscher, Martin; Pingali, Keshav
- 2013 IEEE 27th International Symposium on Parallel and Distributed Processing
Accelerating Irregular Algorithms on GPGPUs Using Fine-Grain Hardware Worklists
conference, December 2014
- Kim, Ji Yun; Batten, Christopher
- 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture
Adaptive Multi-Phase Erase
patent-application, March 2017
- Yang, Nian Niles; Bauche, Alexandra
- US Patent Document 14/929179; 20170060445
Atomic-free irregular computations on GPUs
conference, January 2013
- Nasre, Rupesh; Burtscher, Martin; Pingali, Keshav
- GPGPU-6 Proceedings of the 6th Workshop on General Purpose Processor Using Graphics Processing Units, p. 96-107
Data Structure Store and Data Management
patent-application, October 2016
- Sivananainthaperumal, Anusha; Yasa, Giridhar Appaji Nag; Bakre, Ajay Vijay
- US Patent Document 15/078929; 20160313916
A study of Persistent Threads style GPU programming for GPGPU workloads
conference, May 2012
- Gupta, Kshitij; Stuart, Jeff A.; Owens, John D.
- 2012 Innovative Parallel Computing (InPar)
Fine-grain task aggregation and coordination on GPUs
conference, June 2014
- Orr, Marc S.; Beckmann, Bradford M.; Reinhardt, Steven K.
- 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)