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Title: Prioritizing local and remote memory access in a non-uniform memory access architecture

Abstract

A miss in a cache by a thread in a wavefront is detected. The wavefront includes a plurality of threads that are executing a memory access request concurrently on a corresponding plurality of processor cores. A priority is assigned to the thread based on whether the memory access request is addressed to a local memory or a remote memory. The memory access request for the thread is performed based on the priority. In some cases, the cache is selectively bypassed depending on whether the memory access request is addressed to the local or remote memory. A cache block is requested in response to the miss. The cache block is biased towards a least recently used position in response to requesting the cache block from the local memory and towards a most recently used position in response to requesting the cache block from the remote memory.

Inventors:
; ; ; ;
Issue Date:
Research Org.:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1771644
Patent Number(s):
10838864
Application Number:
15/992,885
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
AC52-07NA27344; B620717
Resource Type:
Patent
Resource Relation:
Patent File Date: 05/30/2018
Country of Publication:
United States
Language:
English

Citation Formats

Boyer, Michael W., Kayiran, Onur, Eckert, Yasuko, Raasch, Steven E., and Shoaib Bin Altaf, Muhammad. Prioritizing local and remote memory access in a non-uniform memory access architecture. United States: N. p., 2020. Web.
Boyer, Michael W., Kayiran, Onur, Eckert, Yasuko, Raasch, Steven E., & Shoaib Bin Altaf, Muhammad. Prioritizing local and remote memory access in a non-uniform memory access architecture. United States.
Boyer, Michael W., Kayiran, Onur, Eckert, Yasuko, Raasch, Steven E., and Shoaib Bin Altaf, Muhammad. Tue . "Prioritizing local and remote memory access in a non-uniform memory access architecture". United States. https://www.osti.gov/servlets/purl/1771644.
@article{osti_1771644,
title = {Prioritizing local and remote memory access in a non-uniform memory access architecture},
author = {Boyer, Michael W. and Kayiran, Onur and Eckert, Yasuko and Raasch, Steven E. and Shoaib Bin Altaf, Muhammad},
abstractNote = {A miss in a cache by a thread in a wavefront is detected. The wavefront includes a plurality of threads that are executing a memory access request concurrently on a corresponding plurality of processor cores. A priority is assigned to the thread based on whether the memory access request is addressed to a local memory or a remote memory. The memory access request for the thread is performed based on the priority. In some cases, the cache is selectively bypassed depending on whether the memory access request is addressed to the local or remote memory. A cache block is requested in response to the miss. The cache block is biased towards a least recently used position in response to requesting the cache block from the local memory and towards a most recently used position in response to requesting the cache block from the remote memory.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Nov 17 00:00:00 EST 2020},
month = {Tue Nov 17 00:00:00 EST 2020}
}

Works referenced in this record:

Instruction and Logic for Adaptive Dataset Priorities in Processor Caches
patent-application, March 2016


Cache Entry Replacement Based on Penalty of Memory Access
patent-application, April 2018


Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance
conference, October 2015