Direct access inter-process shared memory
Abstract
A technique for directly sharing physical memory between processes executing on processor cores is described. The technique includes loading a plurality of processes into the physical memory for execution on a corresponding plurality of processor cores sharing the physical memory. An address space is mapped to each of the processes by populating a first entry in a top level virtual address table for each of the processes. The address space of each of the processes is cross-mapped into each of the processes by populating one or more subsequent entries of the top level virtual address table with the first entry in the top level virtual address table from other processes.
- Inventors:
- Issue Date:
- Research Org.:
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1107593
- Patent Number(s):
- 8566536
- Application Number:
- 12/551,666
- Assignee:
- Sandia Corporation (Albuquerque, NM)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC04-94AL850(X)
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Brightwell, Ronald B, Pedretti, Kevin, and Hudson, Trammell B. Direct access inter-process shared memory. United States: N. p., 2013.
Web.
Brightwell, Ronald B, Pedretti, Kevin, & Hudson, Trammell B. Direct access inter-process shared memory. United States.
Brightwell, Ronald B, Pedretti, Kevin, and Hudson, Trammell B. Tue .
"Direct access inter-process shared memory". United States. https://www.osti.gov/servlets/purl/1107593.
@article{osti_1107593,
title = {Direct access inter-process shared memory},
author = {Brightwell, Ronald B and Pedretti, Kevin and Hudson, Trammell B},
abstractNote = {A technique for directly sharing physical memory between processes executing on processor cores is described. The technique includes loading a plurality of processes into the physical memory for execution on a corresponding plurality of processor cores sharing the physical memory. An address space is mapped to each of the processes by populating a first entry in a top level virtual address table for each of the processes. The address space of each of the processes is cross-mapped into each of the processes by populating one or more subsequent entries of the top level virtual address table with the first entry in the top level virtual address table from other processes.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2013},
month = {10}
}
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