Random access memory immune to single event upset using a T-resistor

Patent · Sun Jan 01 00:00:00 EST 1989

OSTI ID:866861

Ochoa, Jr., Agustin ^[1]

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1. (Vista, CA)

In a random access memory cell, a resistance "T" decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell.

• Research Organization: AT&T
• DOE Contract Number: AC04-76DP00789
• Assignee: United States of America as represented by United States (Washington, DC)
• Patent Number(s): US 4809226
• OSTI ID: 866861
• Country of Publication: United States
• Language: English

Related Subjects

random
access
memory
immune
single
event
upset
t-resistor
cell
resistance
decoupling
network
leg
reduces
errors
caused
interaction
energetic
semiconductor
material
forming
comprises
parallel
legs
containing
series
pair
complementary
transistors
common
gate
connected
node
opposite
formed
resistors
third
resistor
interconnecting
junction
transistor
random access
access memory
cell comprises
semiconductor material
single event
material forming
memory cell
event upset
gate connected
errors caused
cell reduces
decoupling network
/365/