Semiconductor structure and recess formation etch technique
Abstract
A semiconductor structure has a first layer that includes a first semiconductor material and a second layer that includes a second semiconductor material. The first semiconductor material is selectively etchable over the second semiconductor material using a first etching process. The first layer is disposed over the second layer. A recess is disposed at least in the first layer. Also described is a method of forming a semiconductor structure that includes a recess. The method includes etching a region in a first layer using a first etching process. The first layer includes a first semiconductor material. The first etching process stops at a second layer beneath the first layer. The second layer includes a second semiconductor material.
- Inventors:
- Issue Date:
- Research Org.:
- Massachusetts Inst. of Technology (MIT), Cambridge, MA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1343744
- Patent Number(s):
- 9570600
- Application Number:
- 14/442,546
- Assignee:
- Massachusetts Institute of Technology
- Patent Classifications (CPCs):
-
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
- DOE Contract Number:
- AR0000123
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2013 Nov 15
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 36 MATERIALS SCIENCE
Citation Formats
Lu, Bin, Sun, Min, and Palacios, Tomas Apostol. Semiconductor structure and recess formation etch technique. United States: N. p., 2017.
Web.
Lu, Bin, Sun, Min, & Palacios, Tomas Apostol. Semiconductor structure and recess formation etch technique. United States.
Lu, Bin, Sun, Min, and Palacios, Tomas Apostol. Tue .
"Semiconductor structure and recess formation etch technique". United States. https://www.osti.gov/servlets/purl/1343744.
@article{osti_1343744,
title = {Semiconductor structure and recess formation etch technique},
author = {Lu, Bin and Sun, Min and Palacios, Tomas Apostol},
abstractNote = {A semiconductor structure has a first layer that includes a first semiconductor material and a second layer that includes a second semiconductor material. The first semiconductor material is selectively etchable over the second semiconductor material using a first etching process. The first layer is disposed over the second layer. A recess is disposed at least in the first layer. Also described is a method of forming a semiconductor structure that includes a recess. The method includes etching a region in a first layer using a first etching process. The first layer includes a first semiconductor material. The first etching process stops at a second layer beneath the first layer. The second layer includes a second semiconductor material.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Feb 14 00:00:00 EST 2017},
month = {Tue Feb 14 00:00:00 EST 2017}
}
Works referenced in this record:
Nitride-based transistors and methods of fabrication thereof using non-etched contact recesses
patent, January 2006
- Saxler, Adam William; Smith, Richard Peter; Sheppard, Scott
- US Patent Document 6,982,204
Nitride-based transistors with a protective layer and a low-damage recess and methods of fabrication thereof
patent, May 2006
- Sheppard, Scott; Smith, Richard Peter; Ring, Zoltan
- US Patent Document 7,045,404
Two stage plasma etching method for enhancement mode GaN HFET
patent, February 2012
- Burnham, Shawn D.; Boutros, Karim S.
- US Patent Document 8,124,505
Method of manufacturing high frequency device structure
patent, December 2012
- Yoon, Hyung Sup; Min, Byoung-Gue; Ahn, Hokyun
- US Patent Document 8,338,241
Composite passivation process for nitride FET
patent, April 2013
- Heying, Benjamin; Smorchkova, Ioulia; Gambin, Vincent
- US Patent Document 8,431,962
Enhancement mode III-N HEMTs
patent, August 2013
- Mishra, Umesh; Coffie, Robert; Shen, Likun
- US Patent Document 8,519,438
Compound semiconductor device and method of manufacturing the same
patent, May 2016
- Kanamura, Masahito; Kikkawa, Toshihide
- US Patent Document 9,331,190
Method of Group III Metal - Nitride Material Growth Using Metal Organic Vapor Phase Epitaxy
patent-application, October 2011
- Detchprohm, Theeradetch; Zhu, Mingwei; Wetzel, Christian
- US Patent Application 13/087614; 20110254134
V-Gate GaN HEMTs With Engineered Buffer for Normally Off Operation
journal, November 2008
- Chu, Rongming; Chen, Zhen; DenBaars, Steven P.
- IEEE Electron Device Letters, Vol. 29, Issue 11, p. 1184-1186
AlGaN/GaN HEMT With 300-GHz fmax
journal, March 2010
- Chung, J. W.; Hoke, W. E.; Chumbes, E. M.
- IEEE Electron Device Letters, Vol. 31, Issue 3, p. 195-197
Enhancement-Mode GaN MIS-HEMTs With n-GaN/i-AlN/n-GaN Triple Cap Layer and High- k Gate Dielectrics
journal, March 2010
- Kanamura, M.; Ohki, T.; Kikkawa, T.
- IEEE Electron Device Letters, Vol. 31, Issue 3, p. 189-191
Digital etching of III-N materials using a two-step Ar/KOH technique
journal, April 2006
- Keogh, David; Asbeck, Peter; Chung, Theodore
- Journal of Electronic Materials, Vol. 35, Issue 4, p. 771-776
An Etch-Stop Barrier Structure for GaN High-Electron-Mobility Transistors
journal, March 2013
- Lu, Bin; Sun, Min; Palacios, T.
- IEEE Electron Device Letters, Vol. 34, Issue 3, p. 369-371
High-Performance Integrated Dual-Gate AlGaN/GaN Enhancement-Mode Transistor
journal, September 2010
- Lu, Bin; Saadat, Omair Irfan; Palacios, Tomás
- IEEE Electron Device Letters, Vol. 31, Issue 9, p. 990-992
Nitride-based high electron mobility transistors with a GaN spacer
journal, August 2006
- Palacios, T.; Shen, L.; Keller, S.
- Applied Physics Letters, Vol. 89, Issue 7, Article No. 073508
Origin and passivation of fixed charge in atomic layer deposited aluminum oxide gate insulators on chemically treated InGaAs substrates
journal, April 2010
- Shin, Byungha; Weber, Justin R.; Long, Rathnait D.
- Applied Physics Letters, Vol. 96, Issue 15, Article No. 152908
Fabrication of Normally Off AlGaN/GaN MOSFET Using a Self-Terminating Gate Recess Etching Technique
journal, July 2013
- Xu, Zhe; Wang, Jinyan; Liu, Yang
- IEEE Electron Device Letters, Vol. 34, Issue 7, p. 855-857