Memory controller that forces prefetches in response to a present row address change timing constraint
Abstract
An apparatus having a memory controller is described. The memory controller includes prefetch circuitry to prefetch, from a memory, data having a same row address in response to the memory controller's servicing of its request stream being stalled because of a timing constraint that prevents a change in row address. The memory controller also includes a cache to cache the prefetched data. The memory controller also includes circuitry to compare addresses of read requests in the memory controller's request stream against respective addresses of the prefetched data in the cache and to service those of the requests in the memory controller's request stream having a matching address with corresponding ones of the prefetched data in the cache.
- Inventors:
- Issue Date:
- Research Org.:
- Intel Corp., Santa Clara, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1568243
- Patent Number(s):
- 10268585
- Application Number:
- 15/195,887
- Assignee:
- Intel Corporation (Santa Clara, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
- DOE Contract Number:
- B608115
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 06/28/2016
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Ranjan, Ashish, and Kozhikkottu, Vivek. Memory controller that forces prefetches in response to a present row address change timing constraint. United States: N. p., 2019.
Web.
Ranjan, Ashish, & Kozhikkottu, Vivek. Memory controller that forces prefetches in response to a present row address change timing constraint. United States.
Ranjan, Ashish, and Kozhikkottu, Vivek. Tue .
"Memory controller that forces prefetches in response to a present row address change timing constraint". United States. https://www.osti.gov/servlets/purl/1568243.
@article{osti_1568243,
title = {Memory controller that forces prefetches in response to a present row address change timing constraint},
author = {Ranjan, Ashish and Kozhikkottu, Vivek},
abstractNote = {An apparatus having a memory controller is described. The memory controller includes prefetch circuitry to prefetch, from a memory, data having a same row address in response to the memory controller's servicing of its request stream being stalled because of a timing constraint that prevents a change in row address. The memory controller also includes a cache to cache the prefetched data. The memory controller also includes circuitry to compare addresses of read requests in the memory controller's request stream against respective addresses of the prefetched data in the cache and to service those of the requests in the memory controller's request stream having a matching address with corresponding ones of the prefetched data in the cache.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Apr 23 00:00:00 EDT 2019},
month = {Tue Apr 23 00:00:00 EDT 2019}
}