Promoting prefetched data from a cache memory to registers in a processor
Abstract
An electronic device includes a processor having a cache memory, a plurality of physical registers, and a promotion logic functional block. The promotion logic functional block promotes prefetched data from a portion of a cache block in the cache memory into a given physical register, the promoting including storing the prefetched data in the given physical register. Upon encountering a load micro-operation that loads data from the portion of the cache block into a destination physical register, the promotion logic functional block sets the processor so that the prefetched data stored in the given physical register is provided to micro-operations that depend on the load micro-operation.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States); Advanced Micro Devices, Inc., Santa Clara, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1986742
- Patent Number(s):
- 11481331
- Application Number:
- 17/135,832
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- DOE Contract Number:
- AC52-07NA27344; B620717
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 12/28/2020
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Kotra, Jagadish, and Kalamatianos, John. Promoting prefetched data from a cache memory to registers in a processor. United States: N. p., 2022.
Web.
Kotra, Jagadish, & Kalamatianos, John. Promoting prefetched data from a cache memory to registers in a processor. United States.
Kotra, Jagadish, and Kalamatianos, John. Tue .
"Promoting prefetched data from a cache memory to registers in a processor". United States. https://www.osti.gov/servlets/purl/1986742.
@article{osti_1986742,
title = {Promoting prefetched data from a cache memory to registers in a processor},
author = {Kotra, Jagadish and Kalamatianos, John},
abstractNote = {An electronic device includes a processor having a cache memory, a plurality of physical registers, and a promotion logic functional block. The promotion logic functional block promotes prefetched data from a portion of a cache block in the cache memory into a given physical register, the promoting including storing the prefetched data in the given physical register. Upon encountering a load micro-operation that loads data from the portion of the cache block into a destination physical register, the promotion logic functional block sets the processor so that the prefetched data stored in the given physical register is provided to micro-operations that depend on the load micro-operation.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2022},
month = {10}
}
Works referenced in this record:
Fusing Load and ALU Operations
patent-application, December 2003
- Samra, Nicholas G.; Jourdan, Stephan J.; Sager, David J.
- US Patent Application 10/180391; 20030236966
Symmetric Multiprocessor Coherence Mechanism
patent-application, January 2003
- Dhong, Sang Hoo; Hofstee, Harm Peter; Johns, Charles Ray
- US Patent Application 09/895888; 20030005237