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Title: Control flow guided lock address prefetch and filtering

Abstract

A method of prefetching target data includes, in response to detecting a lock-prefixed instruction for execution in a processor, determining a predicted target memory location for the lock-prefixed instruction based on control flow information associating the lock-prefixed instruction with the predicted target memory location. Target data is prefetched from the predicted target memory location to a cache coupled with the processor, and after completion of the prefetching, the lock-prefixed instruction is executed in the processor using the prefetched target data.

Inventors:
;
Issue Date:
Research Org.:
Advanced Micro Devices, Inc., Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1892599
Patent Number(s):
11243884
Application Number:
16/190,111
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
AC52-07NA27344; B620717
Resource Type:
Patent
Resource Relation:
Patent File Date: 11/13/2018
Country of Publication:
United States
Language:
English

Citation Formats

Mashimo, Susumu, and Kalamatianos, John. Control flow guided lock address prefetch and filtering. United States: N. p., 2022. Web.
Mashimo, Susumu, & Kalamatianos, John. Control flow guided lock address prefetch and filtering. United States.
Mashimo, Susumu, and Kalamatianos, John. Tue . "Control flow guided lock address prefetch and filtering". United States. https://www.osti.gov/servlets/purl/1892599.
@article{osti_1892599,
title = {Control flow guided lock address prefetch and filtering},
author = {Mashimo, Susumu and Kalamatianos, John},
abstractNote = {A method of prefetching target data includes, in response to detecting a lock-prefixed instruction for execution in a processor, determining a predicted target memory location for the lock-prefixed instruction based on control flow information associating the lock-prefixed instruction with the predicted target memory location. Target data is prefetched from the predicted target memory location to a cache coupled with the processor, and after completion of the prefetching, the lock-prefixed instruction is executed in the processor using the prefetched target data.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2022},
month = {2}
}

Works referenced in this record:

System and Method for Prefetching Data into a Cache Based on Miss Distance
patent-application, July 2002


Efficient synchronization
journal, May 1997


Multi-Processing in a BIOS Environment
patent-application, December 2004