Per-page control of physical address space distribution among memory modules

Title: Per-page control of physical address space distribution among memory modules

Abstract

Systems, apparatuses, and methods for implementing per-page control of physical address space distribution among memory modules are disclosed. A computing system includes a plurality of processing units coupled to a plurality of memory modules. A determination is made as to which physical address space distribution granularity to implement for physical memory pages allocated for a first data structure. The determination can be made on a per-data-structure basis (e.g., file, page, block, etc.) or on a per-application-basis. A physical address space distribution granularity is encoded as a property of each physical memory page allocated for the first data structure, and physical memory pages of the first data structure distributed across the plurality of memory modules based on a selected physical address space distribution granularity. Page table entries (PTEs) may be annotated with the selected physical address space distribution granularity, using an addressing mapping granularity (AMG) field of a page table entry, where the granularity may be, for example, a fine-grain distribution granularity or a coarse-grain distribution granularity.

Inventors:: Jayasena, Nuwan S.; Kim, Hyojong; Kim, Hyesoon

Issue Date:: 2019-05-07

Research Org.:: Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1568306

Patent Number(s):: 10282309

Application Number:: 15/441,532

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F12/0623 - {for memory modules}
G06F2212/652 - Page size control
G06F2212/657 - Virtual address space management
G06F12/1027 - using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F2212/1024 - Latency reduction
G06F2212/68 - Details of translation look-aside buffer [TLB]
G06F15/7821 - {Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory}
G06F12/1009 - using page tables, e.g. page table structures
G06F2212/502 - using adaptive policy
G06F2212/656 - Address space sharing
G06F12/0284 - {Multiple user address space allocation, e.g. using different base addresses
G06F12/109 - for multiple virtual address spaces, e.g. segmentation
G06F12/0607 - {Interleaved addressing}

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DOE Contract Number:: AC52-07NA27344; B608045

Resource Type:: Patent

Resource Relation:: Patent File Date: 02/24/2017

Country of Publication:: United States

Language:: English

Citation Formats


                    Jayasena, Nuwan S., Kim, Hyojong, and Kim, Hyesoon. Per-page control of physical address space distribution among memory modules.  United States: N. p., 2019. 
        Web.

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                    Jayasena, Nuwan S., Kim, Hyojong, & Kim, Hyesoon. Per-page control of physical address space distribution among memory modules.  United States.

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                    Jayasena, Nuwan S., Kim, Hyojong, and Kim, Hyesoon. Tue .  
        "Per-page control of physical address space distribution among memory modules".  United States.  https://www.osti.gov/servlets/purl/1568306.

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@article{osti_1568306,

  title        = {Per-page control of physical address space distribution among memory modules},

  author       = {Jayasena, Nuwan S. and Kim, Hyojong and Kim, Hyesoon},

  abstractNote = {Systems, apparatuses, and methods for implementing per-page control of physical address space distribution among memory modules are disclosed. A computing system includes a plurality of processing units coupled to a plurality of memory modules. A determination is made as to which physical address space distribution granularity to implement for physical memory pages allocated for a first data structure. The determination can be made on a per-data-structure basis (e.g., file, page, block, etc.) or on a per-application-basis. A physical address space distribution granularity is encoded as a property of each physical memory page allocated for the first data structure, and physical memory pages of the first data structure distributed across the plurality of memory modules based on a selected physical address space distribution granularity. Page table entries (PTEs) may be annotated with the selected physical address space distribution granularity, using an addressing mapping granularity (AMG) field of a page table entry, where the granularity may be, for example, a fine-grain distribution granularity or a coarse-grain distribution granularity.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2019},

  month        = {5}

}

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Similar Records

Title: Per-page control of physical address space distribution among memory modules

Abstract

Citation Formats

Method and apparatus for dynamically adjusting page size in a virtual memory range patent, June 2010

Method and mechanism for efficiently creating large virtual memory pages in a multiple page size environment patent, October 2008

Virtual to physical address translation scheme with granularity hint for identifying subsequent pages to be accessed patent, September 1995

Translation look-aside buffer including a single page size translation unit patent, May 1998

Variable page size translation lookaside buffer patent, June 1996

Method, system and computer program product for virtual memory support for managing translation look aside buffers with multiple page size support patent, August 2000

Prefetching in a virtual memory system based upon repeated accesses across page boundaries patent, January 2011

Memory addressing controlled by PTE fields patent, September 2010

Optimizing TLB entries for mixed page size storage in contiguous memory patent, April 2013

Translation lookaside buffer supporting multiple page sizes patent, May 1999

Processing system implementing multiple page size memory organization with multiple translation lookaside buffers having differing characteristics patent, September 2010

Extended page size using aggregated small pages patent, June 2012

Efficient address interleaving with simultaneous multiple locality options patent, May 2003

Method and apparatus for dynamically adjusting page size in a virtual memory range
patent, June 2010

Method and mechanism for efficiently creating large virtual memory pages in a multiple page size environment
patent, October 2008

Virtual to physical address translation scheme with granularity hint for identifying subsequent pages to be accessed
patent, September 1995

Translation look-aside buffer including a single page size translation unit
patent, May 1998

Variable page size translation lookaside buffer
patent, June 1996

Method, system and computer program product for virtual memory support for managing translation look aside buffers with multiple page size support
patent, August 2000

Prefetching in a virtual memory system based upon repeated accesses across page boundaries
patent, January 2011

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patent, September 2010

Optimizing TLB entries for mixed page size storage in contiguous memory
patent, April 2013

Translation lookaside buffer supporting multiple page sizes
patent, May 1999

Processing system implementing multiple page size memory organization with multiple translation lookaside buffers having differing characteristics
patent, September 2010

Extended page size using aggregated small pages
patent, June 2012

Efficient address interleaving with simultaneous multiple locality options
patent, May 2003