Per-page control of physical address space distribution among memory modules
Abstract
Systems, apparatuses, and methods for implementing per-page control of physical address space distribution among memory modules are disclosed. A computing system includes a plurality of processing units coupled to a plurality of memory modules. A determination is made as to which physical address space distribution granularity to implement for physical memory pages allocated for a first data structure. The determination can be made on a per-data-structure basis (e.g., file, page, block, etc.) or on a per-application-basis. A physical address space distribution granularity is encoded as a property of each physical memory page allocated for the first data structure, and physical memory pages of the first data structure distributed across the plurality of memory modules based on a selected physical address space distribution granularity. Page table entries (PTEs) may be annotated with the selected physical address space distribution granularity, using an addressing mapping granularity (AMG) field of a page table entry, where the granularity may be, for example, a fine-grain distribution granularity or a coarse-grain distribution granularity.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1568306
- Patent Number(s):
- 10282309
- Application Number:
- 15/441,532
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC52-07NA27344; B608045
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 02/24/2017
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Jayasena, Nuwan S., Kim, Hyojong, and Kim, Hyesoon. Per-page control of physical address space distribution among memory modules. United States: N. p., 2019.
Web.
Jayasena, Nuwan S., Kim, Hyojong, & Kim, Hyesoon. Per-page control of physical address space distribution among memory modules. United States.
Jayasena, Nuwan S., Kim, Hyojong, and Kim, Hyesoon. Tue .
"Per-page control of physical address space distribution among memory modules". United States. https://www.osti.gov/servlets/purl/1568306.
@article{osti_1568306,
title = {Per-page control of physical address space distribution among memory modules},
author = {Jayasena, Nuwan S. and Kim, Hyojong and Kim, Hyesoon},
abstractNote = {Systems, apparatuses, and methods for implementing per-page control of physical address space distribution among memory modules are disclosed. A computing system includes a plurality of processing units coupled to a plurality of memory modules. A determination is made as to which physical address space distribution granularity to implement for physical memory pages allocated for a first data structure. The determination can be made on a per-data-structure basis (e.g., file, page, block, etc.) or on a per-application-basis. A physical address space distribution granularity is encoded as a property of each physical memory page allocated for the first data structure, and physical memory pages of the first data structure distributed across the plurality of memory modules based on a selected physical address space distribution granularity. Page table entries (PTEs) may be annotated with the selected physical address space distribution granularity, using an addressing mapping granularity (AMG) field of a page table entry, where the granularity may be, for example, a fine-grain distribution granularity or a coarse-grain distribution granularity.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {5}
}
Works referenced in this record:
Method and apparatus for dynamically adjusting page size in a virtual memory range
patent, June 2010
- Hepkin, David; Swanberg, Randal
- US Patent Document 7,747,838
Method and mechanism for efficiently creating large virtual memory pages in a multiple page size environment
patent, October 2008
- Burugula, Ramanjaneya Sarma; Hepkin, David; Jann, Joefon
- US Patent Document 7,437,529
Virtual to physical address translation scheme with granularity hint for identifying subsequent pages to be accessed
patent, September 1995
- Sites, Richard; Witek, Richard T.
- US Patent Document 5,454,091
Translation look-aside buffer including a single page size translation unit
patent, May 1998
- Hammond, Gary N.
- US Patent Document 5,752,275
Variable page size translation lookaside buffer
patent, June 1996
- Hsu, Peter Y.; Scanlon, Joseph T.; Ciavaglia, Steve J.
- US Patent Document 5,526,504
Method, system and computer program product for virtual memory support for managing translation look aside buffers with multiple page size support
patent, August 2000
- Ganapathy, Narayanan; Stevens, Luis F.; Schimmel, Curt F.
- US Patent Document 6,112,285
Prefetching in a virtual memory system based upon repeated accesses across page boundaries
patent, January 2011
- Anand, Vaijayanthimala K.; Johnson, Sandra K.
- US Patent Document 7,873,792
Memory addressing controlled by PTE fields
patent, September 2010
- Van Dyke, James M.; Edmondson, John H.
- US Patent Document 7,805,587
Optimizing TLB entries for mixed page size storage in contiguous memory
patent, April 2013
- Chen, Dong; Gara, Alan G.; Giampapa, Mark E.
- US Patent Document 8,429,377
Translation lookaside buffer supporting multiple page sizes
patent, May 1999
- Shinbo, Toshinobu; Tachibana, Suguru; Narita, Susumu
- US Patent Document 5,907,867
Processing system implementing multiple page size memory organization with multiple translation lookaside buffers having differing characteristics
patent, September 2010
- Stecher, Brian John
- US Patent Document 7,793,070
Extended page size using aggregated small pages
patent, June 2012
- Hohmuth, Michael P.; Dannowski, Uwe M.; Biemueller, Sebastian Martin
- US Patent Document 8,195,917
Efficient address interleaving with simultaneous multiple locality options
patent, May 2003
- Kessler, Richard E.
- US Patent Document 6,567,900