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Title: Method for fabricating transistors using crystalline silicon devices on glass

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.
  1. (Menlo Park, CA)
Issue Date:
OSTI Identifier:
Regents of University of California (Oakland, CA) LLNL
Patent Number(s):
US 5663078
Contract Number:
Research Org:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Country of Publication:
United States
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