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Title: High voltage semiconductor devices and methods of making the devices

Abstract

Metal-oxide-semiconductor field-effect transistor (MOSFET) devices are described which have a p-type region between the p-type well regions of the device. The p-type region can be either floating or connected to the p-type well regions by additional p-type regions. MOSFET devices are also described which have one or more p-type regions connecting the p-type well regions of the device. The p-type well regions can be arranged in a various geometric arrangements including square, diamond and hexagonal. Methods of making the devices are also described.

Inventors:
; ; ;
Issue Date:
Research Org.:
Monolith Semiconductor Inc., Round Rock, TX (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1471407
Patent Number(s):
10,062,749
Application Number:
14/303,019
Assignee:
Monolith Semiconductor Inc. (Round Rock, TX)
DOE Contract Number:  
AR0000442
Resource Type:
Patent
Resource Relation:
Patent File Date: 2014 Jun 12
Country of Publication:
United States
Language:
English
Subject:
36 MATERIALS SCIENCE

Citation Formats

Chatty, Kiran, Matocha, Kevin, Banerjee, Sujit, and Rowland, Larry Burton. High voltage semiconductor devices and methods of making the devices. United States: N. p., 2018. Web.
Chatty, Kiran, Matocha, Kevin, Banerjee, Sujit, & Rowland, Larry Burton. High voltage semiconductor devices and methods of making the devices. United States.
Chatty, Kiran, Matocha, Kevin, Banerjee, Sujit, and Rowland, Larry Burton. Tue . "High voltage semiconductor devices and methods of making the devices". United States. https://www.osti.gov/servlets/purl/1471407.
@article{osti_1471407,
title = {High voltage semiconductor devices and methods of making the devices},
author = {Chatty, Kiran and Matocha, Kevin and Banerjee, Sujit and Rowland, Larry Burton},
abstractNote = {Metal-oxide-semiconductor field-effect transistor (MOSFET) devices are described which have a p-type region between the p-type well regions of the device. The p-type region can be either floating or connected to the p-type well regions by additional p-type regions. MOSFET devices are also described which have one or more p-type regions connecting the p-type well regions of the device. The p-type well regions can be arranged in a various geometric arrangements including square, diamond and hexagonal. Methods of making the devices are also described.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {8}
}

Patent:

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