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Title: High voltage semiconductor devices and methods of making the devices

Abstract

A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.

Inventors:
; ;
Issue Date:
Research Org.:
Monolith Semiconductor Inc., Round Rock, TX (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1417850
Patent Number(s):
9,876,104
Application Number:
15/412,462
Assignee:
Monolith Semiconductor Inc. (Round Rock, TX)
DOE Contract Number:  
AR0000442
Resource Type:
Patent
Resource Relation:
Patent File Date: 2017 Jan 23
Country of Publication:
United States
Language:
English
Subject:
36 MATERIALS SCIENCE

Citation Formats

Matocha, Kevin, Chatty, Kiran, and Banerjee, Sujit. High voltage semiconductor devices and methods of making the devices. United States: N. p., 2018. Web.
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Matocha, Kevin, Chatty, Kiran, & Banerjee, Sujit. High voltage semiconductor devices and methods of making the devices. United States.
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Matocha, Kevin, Chatty, Kiran, and Banerjee, Sujit. Tue . "High voltage semiconductor devices and methods of making the devices". United States. https://www.osti.gov/servlets/purl/1417850.
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@article{osti_1417850,
title = {High voltage semiconductor devices and methods of making the devices},
author = {Matocha, Kevin and Chatty, Kiran and Banerjee, Sujit},
abstractNote = {A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {1}
}
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Works referenced in this record:

Low Loss Sic Mosfet
patent-application, October 2013

4H-SiC N-Channel JFET for Operation in High-Temperature Environments
journal, November 2014

  • Lien, Wei-Chen; Damrongplasit, Nattapol; Paredes, John H.
  • IEEE Journal of the Electron Devices Society, Vol. 2, Issue 6, p. 164-167
  • DOI: 10.1109/JEDS.2014.2355132

Improvement of the electrical safe operating area of a DMOS transistor during ESD events
conference, April 2009

  • Podgaynaya, Alevtina; Pogany, Dionyz; Gornik, Erich
  • Reliability Physics Symposium, 2009 IEEE International
  • DOI: 10.1109/IRPS.2009.5173293

Influence of Anode Layout on the Performance of SiC JBS Diodes
journal, May 2012

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