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Title: Heap/stack guard pages using a wakeup unit

Abstract

A method and system for providing a memory access check on a processor including the steps of detecting accesses to a memory device including level-1 cache using a wakeup unit. The method includes invalidating level-1 cache ranges corresponding to a guard page, and configuring a plurality of wakeup address compare (WAC) registers to allow access to selected WAC registers. The method selects one of the plurality of WAC registers, and sets up a WAC register related to the guard page. The method configures the wakeup unit to interrupt on access of the selected WAC register. The method detects access of the memory device using the wakeup unit when a guard page is violated. The method generates an interrupt to the core using the wakeup unit, and determines the source of the interrupt. The method detects the activated WAC registers assigned to the violated guard page, and initiates a response.

Inventors:
; ;
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1129892
Patent Number(s):
8,713,294
Application Number:
12/696,817
Assignee:
International Business Machines Corporation (Armonk, NY)
DOE Contract Number:  
B554331
Resource Type:
Patent
Resource Relation:
Patent File Date: 2010 Jan 29
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Gooding, Thomas M, Satterfield, David L, and Steinmacher-Burow, Burkhard. Heap/stack guard pages using a wakeup unit. United States: N. p., 2014. Web.
Gooding, Thomas M, Satterfield, David L, & Steinmacher-Burow, Burkhard. Heap/stack guard pages using a wakeup unit. United States.
Gooding, Thomas M, Satterfield, David L, and Steinmacher-Burow, Burkhard. Tue . "Heap/stack guard pages using a wakeup unit". United States. https://www.osti.gov/servlets/purl/1129892.
@article{osti_1129892,
title = {Heap/stack guard pages using a wakeup unit},
author = {Gooding, Thomas M and Satterfield, David L and Steinmacher-Burow, Burkhard},
abstractNote = {A method and system for providing a memory access check on a processor including the steps of detecting accesses to a memory device including level-1 cache using a wakeup unit. The method includes invalidating level-1 cache ranges corresponding to a guard page, and configuring a plurality of wakeup address compare (WAC) registers to allow access to selected WAC registers. The method selects one of the plurality of WAC registers, and sets up a WAC register related to the guard page. The method configures the wakeup unit to interrupt on access of the selected WAC register. The method detects access of the memory device using the wakeup unit when a guard page is violated. The method generates an interrupt to the core using the wakeup unit, and determines the source of the interrupt. The method detects the activated WAC registers assigned to the violated guard page, and initiates a response.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2014},
month = {4}
}

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Works referenced in this record:

Program stack handling
patent-application, October 2006


Efficient and flexible architectural support for dynamic monitoring
journal, March 2005

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