Single instruction multiple data page table walk scheduling at input output memory management unit

Patent · Tue Oct 08 00:00:00 EDT 2019

OSTI ID:1576446

Basu, Arkaprava; Van Tassell, Eric; Oskin, Mark; Cox, Guilherme; Loh, Gabriel

A data processing system includes a memory and an input output memory management unit that is connected to the memory. The input output memory management unit is adapted to receive batches of address translation requests. The input output memory management unit has instructions that identify, from among the batches of address translation requests, a later batch having a lower number of memory access requests than an earlier batch, and selectively schedules access to a page table walker for each address translation request of a batch.

• Research Organization: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC52-07NA27344; B620717
• Assignee: Advanced Micro Devices, Inc. (Santa Clara, CA)
• Patent Number(s): 10,437,736
• Application Number: 15/852,442
• OSTI ID: 1576446
• Resource Relation: Patent File Date: 2017 Dec 22
• Country of Publication: United States
• Language: English