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Title: Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers

Abstract

A technique for speculatively executing load-dependent instructions includes detecting that a memory ordering consistency queue is full for a completed load instruction. The technique also includes storing data loaded by the completed load instruction into a storage location for storing data when the memory ordering consistency queue is full. The technique further includes speculatively executing instructions that are dependent on the completed load instruction. The technique also includes in response to a slot becoming available in the memory ordering consistency queue, replaying the load instruction. The technique further includes in response to receiving loaded data for the replayed load instruction, testing for a data mis-speculation by comparing the loaded data for the replayed load instruction with the data loaded by the completed load instruction that is stored in the storage location.

Inventors:
; ; ;
Issue Date:
Research Org.:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States); Advanced Micro Devices, Inc., Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1840420
Patent Number(s):
11113065
Application Number:
16/671,097
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
AC52-07NA27344; B620717
Resource Type:
Patent
Resource Relation:
Patent File Date: 10/31/2019
Country of Publication:
United States
Language:
English

Citation Formats

Kalamatianos, John, Mashimo, Susumu, Ramani, Krishnan V., and Bingham, Scott Thomas. Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers. United States: N. p., 2021. Web.
Kalamatianos, John, Mashimo, Susumu, Ramani, Krishnan V., & Bingham, Scott Thomas. Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers. United States.
Kalamatianos, John, Mashimo, Susumu, Ramani, Krishnan V., and Bingham, Scott Thomas. Tue . "Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers". United States. https://www.osti.gov/servlets/purl/1840420.
@article{osti_1840420,
title = {Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers},
author = {Kalamatianos, John and Mashimo, Susumu and Ramani, Krishnan V. and Bingham, Scott Thomas},
abstractNote = {A technique for speculatively executing load-dependent instructions includes detecting that a memory ordering consistency queue is full for a completed load instruction. The technique also includes storing data loaded by the completed load instruction into a storage location for storing data when the memory ordering consistency queue is full. The technique further includes speculatively executing instructions that are dependent on the completed load instruction. The technique also includes in response to a slot becoming available in the memory ordering consistency queue, replaying the load instruction. The technique further includes in response to receiving loaded data for the replayed load instruction, testing for a data mis-speculation by comparing the loaded data for the replayed load instruction with the data loaded by the completed load instruction that is stored in the storage location.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2021},
month = {9}
}

Works referenced in this record:

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patent-application, April 2019


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Non-Speculative Load-Load Reordering in TSO
conference, June 2017


Method and apparatus for facilitating speculative loads in a multiprocessor system
patent-application, December 2002


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conference, October 2018


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patent-application, August 2012


System, Apparatus And Method For Symbolic Store Address Generation For Data-Parallel Processor
patent-application, October 2020