Single instruction multiple data page table walk scheduling at input output memory management unit
Abstract
A data processing system includes a memory and an input output memory management unit that is connected to the memory. The input output memory management unit is adapted to receive batches of address translation requests. The input output memory management unit has instructions that identify, from among the batches of address translation requests, a later batch having a lower number of memory access requests than an earlier batch, and selectively schedules access to a page table walker for each address translation request of a batch.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1576446
- Patent Number(s):
- 10437736
- Application Number:
- 15/852,442
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC52-07NA27344; B620717
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2017 Dec 22
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Basu, Arkaprava, Van Tassell, Eric, Oskin, Mark, Cox, Guilherme, and Loh, Gabriel. Single instruction multiple data page table walk scheduling at input output memory management unit. United States: N. p., 2019.
Web.
Basu, Arkaprava, Van Tassell, Eric, Oskin, Mark, Cox, Guilherme, & Loh, Gabriel. Single instruction multiple data page table walk scheduling at input output memory management unit. United States.
Basu, Arkaprava, Van Tassell, Eric, Oskin, Mark, Cox, Guilherme, and Loh, Gabriel. Tue .
"Single instruction multiple data page table walk scheduling at input output memory management unit". United States. https://www.osti.gov/servlets/purl/1576446.
@article{osti_1576446,
title = {Single instruction multiple data page table walk scheduling at input output memory management unit},
author = {Basu, Arkaprava and Van Tassell, Eric and Oskin, Mark and Cox, Guilherme and Loh, Gabriel},
abstractNote = {A data processing system includes a memory and an input output memory management unit that is connected to the memory. The input output memory management unit is adapted to receive batches of address translation requests. The input output memory management unit has instructions that identify, from among the batches of address translation requests, a later batch having a lower number of memory access requests than an earlier batch, and selectively schedules access to a page table walker for each address translation request of a batch.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {10}
}
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Efficient performance based scheduling mechanism for handling multiple TLB operations
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