Single instruction multiple data page table walk scheduling at input output memory management unit

Basu, Arkaprava; Van Tassell, Eric; Oskin, Mark; Cox, Guilherme; Loh, Gabriel

Title: Single instruction multiple data page table walk scheduling at input output memory management unit

Abstract

A data processing system includes a memory and an input output memory management unit that is connected to the memory. The input output memory management unit is adapted to receive batches of address translation requests. The input output memory management unit has instructions that identify, from among the batches of address translation requests, a later batch having a lower number of memory access requests than an earlier batch, and selectively schedules access to a page table walker for each address translation request of a batch.

Inventors:: Basu, Arkaprava; Van Tassell, Eric; Oskin, Mark; Cox, Guilherme; Loh, Gabriel

Issue Date:: 2019-10-08

Research Org.:: Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1576446

Patent Number(s):: 10437736

Application Number:: 15/852,442

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F13/4282 - {on a serial bus, e.g. I2C bus, SPI bus
G06F2212/684 - TLB miss handling
G06F12/1027 - using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F2212/68 - Details of translation look-aside buffer [TLB]
G06F2212/1024 - Latency reduction
G06F9/3004 - {to perform operations on memory}
G06F2212/65 - Details of virtual memory and virtual address translation
G06F12/1009 - using page tables, e.g. page table structures
G06F2212/1048 - Scalability
G06F2213/0026 - PCI express
G06F9/3887 - {controlled by a single instruction, e.g. SIMD}
G06F2212/681 - Multi-level TLB, e.g. microTLB and main TLB
G06F13/4022 - {using switching circuits, e.g. switching matrix, connection or expansion network
G06F12/1081 - for peripheral access to main memory, e.g. direct memory access [DMA]
G06F9/4843 - {by program, e.g. task dispatcher, supervisor, operating system}

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DOE Contract Number:: AC52-07NA27344; B620717

Resource Type:: Patent

Resource Relation:: Patent File Date: 2017 Dec 22

Country of Publication:: United States

Language:: English

Citation Formats


                    Basu, Arkaprava, Van Tassell, Eric, Oskin, Mark, Cox, Guilherme, and Loh, Gabriel. Single instruction multiple data page table walk scheduling at input output memory management unit.  United States: N. p., 2019. 
        Web.

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                    Basu, Arkaprava, Van Tassell, Eric, Oskin, Mark, Cox, Guilherme, & Loh, Gabriel. Single instruction multiple data page table walk scheduling at input output memory management unit.  United States.

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                    Basu, Arkaprava, Van Tassell, Eric, Oskin, Mark, Cox, Guilherme, and Loh, Gabriel. Tue .  
        "Single instruction multiple data page table walk scheduling at input output memory management unit".  United States.  https://www.osti.gov/servlets/purl/1576446.

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@article{osti_1576446,

  title        = {Single instruction multiple data page table walk scheduling at input output memory management unit},

  author       = {Basu, Arkaprava and Van Tassell, Eric and Oskin, Mark and Cox, Guilherme and Loh, Gabriel},

  abstractNote = {A data processing system includes a memory and an input output memory management unit that is connected to the memory. The input output memory management unit is adapted to receive batches of address translation requests. The input output memory management unit has instructions that identify, from among the batches of address translation requests, a later batch having a lower number of memory access requests than an earlier batch, and selectively schedules access to a page table walker for each address translation request of a batch.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2019},

  month        = {10}

}

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Works referenced in this record:

Paged memory management unit having variable number of translation table levels
patent, August 1988

Keshlear, William M.; Moyer, William C.; Zolnowsky, John E.
US Patent Document 4,763,250
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=4763250

Efficient performance based scheduling mechanism for handling multiple TLB operations
patent, April 2004

Lee, Allisa Chiao-Er; Mathews, Gregory S.
US Patent Document 6,728,800
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6728800

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Title: Single instruction multiple data page table walk scheduling at input output memory management unit

Abstract

Citation Formats

Paged memory management unit having variable number of translation table levels patent, August 1988

Efficient performance based scheduling mechanism for handling multiple TLB operations patent, April 2004

Paged memory management unit having variable number of translation table levels
patent, August 1988

Efficient performance based scheduling mechanism for handling multiple TLB operations
patent, April 2004