Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers
Abstract
A technique for speculatively executing load-dependent instructions includes detecting that a memory ordering consistency queue is full for a completed load instruction. The technique also includes storing data loaded by the completed load instruction into a storage location for storing data when the memory ordering consistency queue is full. The technique further includes speculatively executing instructions that are dependent on the completed load instruction. The technique also includes in response to a slot becoming available in the memory ordering consistency queue, replaying the load instruction. The technique further includes in response to receiving loaded data for the replayed load instruction, testing for a data mis-speculation by comparing the loaded data for the replayed load instruction with the data loaded by the completed load instruction that is stored in the storage location.
- Inventors:
- Publication Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States); Advanced Micro Devices, Inc., Santa Clara, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1840420
- Patent Number(s):
- 11,113,065
- Application Number:
- 16/671,097
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- DOE Contract Number:
- AC52-07NA27344; B620717
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 10/31/2019
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Kalamatianos, John, Mashimo, Susumu, Ramani, Krishnan V., and Bingham, Scott Thomas. Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers. United States: N. p., 2021.
Web.
Kalamatianos, John, Mashimo, Susumu, Ramani, Krishnan V., & Bingham, Scott Thomas. Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers. United States.
Kalamatianos, John, Mashimo, Susumu, Ramani, Krishnan V., and Bingham, Scott Thomas. 2021.
"Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers". United States. https://www.osti.gov/servlets/purl/1840420.
@article{osti_1840420,
title = {Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers},
author = {Kalamatianos, John and Mashimo, Susumu and Ramani, Krishnan V. and Bingham, Scott Thomas},
abstractNote = {A technique for speculatively executing load-dependent instructions includes detecting that a memory ordering consistency queue is full for a completed load instruction. The technique also includes storing data loaded by the completed load instruction into a storage location for storing data when the memory ordering consistency queue is full. The technique further includes speculatively executing instructions that are dependent on the completed load instruction. The technique also includes in response to a slot becoming available in the memory ordering consistency queue, replaying the load instruction. The technique further includes in response to receiving loaded data for the replayed load instruction, testing for a data mis-speculation by comparing the loaded data for the replayed load instruction with the data loaded by the completed load instruction that is stored in the storage location.},
doi = {},
url = {https://www.osti.gov/biblio/1840420},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Sep 07 00:00:00 EDT 2021},
month = {Tue Sep 07 00:00:00 EDT 2021}
}
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