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Title: Memory hierarchy using page-based compression

Abstract

A system includes a device coupleable to a first memory. The device includes a second memory to cache data from the first memory. The second memory is to store a set of compressed pages of the first memory and a set of page descriptors. Each compressed page includes a set of compressed data blocks. Each page descriptor represents a corresponding page and includes a set of location identifiers that identify the locations of the compressed data blocks of the corresponding page in the second memory. The device further includes compression logic to compress data blocks of a page to be stored to the second memory and decompression logic to decompress compressed data blocks of a page accessed from the second memory.

Inventors:
;
Issue Date:
Research Org.:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1840497
Patent Number(s):
11132300
Application Number:
13/939,380
Assignee:
Advanced Micro Devices, Inc. (Sunnyvale, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
AC52-07NA27344; B600716
Resource Type:
Patent
Resource Relation:
Patent File Date: 07/11/2013
Country of Publication:
United States
Language:
English

Citation Formats

Loh, Gabriel H., and O'Connor, James M. Memory hierarchy using page-based compression. United States: N. p., 2021. Web.
Loh, Gabriel H., & O'Connor, James M. Memory hierarchy using page-based compression. United States.
Loh, Gabriel H., and O'Connor, James M. Tue . "Memory hierarchy using page-based compression". United States. https://www.osti.gov/servlets/purl/1840497.
@article{osti_1840497,
title = {Memory hierarchy using page-based compression},
author = {Loh, Gabriel H. and O'Connor, James M.},
abstractNote = {A system includes a device coupleable to a first memory. The device includes a second memory to cache data from the first memory. The second memory is to store a set of compressed pages of the first memory and a set of page descriptors. Each compressed page includes a set of compressed data blocks. Each page descriptor represents a corresponding page and includes a set of location identifiers that identify the locations of the compressed data blocks of the corresponding page in the second memory. The device further includes compression logic to compress data blocks of a page to be stored to the second memory and decompression logic to decompress compressed data blocks of a page accessed from the second memory.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2021},
month = {9}
}

Works referenced in this record:

Memory Devices and Systems Including Multi-Speed Access of Memory Modules
patent-application, November 2010


Compressing data in a cache memory
patent-application, March 2006


Bus Attached Compressed Random Access Memory
patent-application, October 2009


Compressed cache lines incorporating embedded prefetch history data
patent-application, December 2005


Preventing Writeback Race in Multiple Core Processors
patent-application, December 2008


Cache memory
patent-application, October 2008


Dram Cache with Tags and Data Jointly Stored in Physical Rows
patent-application, May 2013


Data caching with a partially compressed cache
patent, November 2001


Adaptive cache compression system
patent-application, May 2006