Memory hierarchy using page-based compression

Loh, Gabriel H.; O'Connor, James M.

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Title: Memory hierarchy using page-based compression

Abstract

A system includes a device coupleable to a first memory. The device includes a second memory to cache data from the first memory. The second memory is to store a set of compressed pages of the first memory and a set of page descriptors. Each compressed page includes a set of compressed data blocks. Each page descriptor represents a corresponding page and includes a set of location identifiers that identify the locations of the compressed data blocks of the corresponding page in the second memory. The device further includes compression logic to compress data blocks of a page to be stored to the second memory and decompression logic to decompress compressed data blocks of a page accessed from the second memory.

Inventors:: Loh, Gabriel H.; O'Connor, James M.

Issue Date:: 2021-09-28

Research Org.:: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1840497

Patent Number(s):: 11132300

Application Number:: 13/939,380

Assignee:: Advanced Micro Devices, Inc. (Sunnyvale, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F12/023 - {Free address space management}
G06F12/0868 - Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
G06F2212/401 - Compressed data

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DOE Contract Number:: AC52-07NA27344; B600716

Resource Type:: Patent

Resource Relation:: Patent File Date: 07/11/2013

Country of Publication:: United States

Language:: English

Citation Formats


                    Loh, Gabriel H., and O'Connor, James M. Memory hierarchy using page-based compression.  United States: N. p., 2021. 
        Web.

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                    Loh, Gabriel H., & O'Connor, James M. Memory hierarchy using page-based compression.  United States.

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                    Loh, Gabriel H., and O'Connor, James M. Tue .  
        "Memory hierarchy using page-based compression".  United States.  https://www.osti.gov/servlets/purl/1840497.

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@article{osti_1840497,

  title        = {Memory hierarchy using page-based compression},

  author       = {Loh, Gabriel H. and O'Connor, James M.},

  abstractNote = {A system includes a device coupleable to a first memory. The device includes a second memory to cache data from the first memory. The second memory is to store a set of compressed pages of the first memory and a set of page descriptors. Each compressed page includes a set of compressed data blocks. Each page descriptor represents a corresponding page and includes a set of location identifiers that identify the locations of the compressed data blocks of the corresponding page in the second memory. The device further includes compression logic to compress data blocks of a page to be stored to the second memory and decompression logic to decompress compressed data blocks of a page accessed from the second memory.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2021},

  month        = {9}

}

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Works referenced in this record:

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patent-application, November 2010

Maheshwari, Dinesh
US Patent Application 12/818304; 20100293325
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Compressing data in a cache memory
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Newburn, Chris J.; Huggahalli, Ram; Hum, Herbert
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Similar Records

Title: Memory hierarchy using page-based compression

Abstract

Citation Formats

Memory Devices and Systems Including Multi-Speed Access of Memory Modules patent-application, November 2010

Compressing data in a cache memory patent-application, March 2006

System and method for using a compressed main memory based on degree of compressibility patent-application, February 2004

Bus Attached Compressed Random Access Memory patent-application, October 2009

Compressed cache lines incorporating embedded prefetch history data patent-application, December 2005

Preventing Writeback Race in Multiple Core Processors patent-application, December 2008

Parallel Compression/Decompression System and Method for Implementation of In-Memory Compressed Cache Improving Storage Density and Access Speed for Industry Standard Memory Subsystems and In-Line Memory Modules patent, February 2003

Cache memory patent-application, October 2008

Dram Cache with Tags and Data Jointly Stored in Physical Rows patent-application, May 2013

Method for maintaining consistent states of a file system and for creating user-accessible read-only copies of a file system patent, October 1998

Data caching with a partially compressed cache patent, November 2001

Multi-processor computing system that employs compressed cache lines' worth of information and processor capable of use in said system patent, August 2007

Adaptive cache compression system patent-application, May 2006

Memory Devices and Systems Including Multi-Speed Access of Memory Modules
patent-application, November 2010

Compressing data in a cache memory
patent-application, March 2006

System and method for using a compressed main memory based on degree of compressibility
patent-application, February 2004

Bus Attached Compressed Random Access Memory
patent-application, October 2009

Compressed cache lines incorporating embedded prefetch history data
patent-application, December 2005

Preventing Writeback Race in Multiple Core Processors
patent-application, December 2008

Parallel Compression/Decompression System and Method for Implementation of In-Memory Compressed Cache Improving Storage Density and Access Speed for Industry Standard Memory Subsystems and In-Line Memory Modules
patent, February 2003

Cache memory
patent-application, October 2008

Dram Cache with Tags and Data Jointly Stored in Physical Rows
patent-application, May 2013

Method for maintaining consistent states of a file system and for creating user-accessible read-only copies of a file system
patent, October 1998

Data caching with a partially compressed cache
patent, November 2001

Multi-processor computing system that employs compressed cache lines' worth of information and processor capable of use in said system
patent, August 2007

Adaptive cache compression system
patent-application, May 2006