Identification of defects in SOI (silicon-on-insulator) wafers
Defects and metal contamination in device areas of silicon integrated circuits (IC) can limit yield in IC fabrication. We describe an electrochemical method for identification of structural defects and metal contamination in low-doped n-type silicon (dopant concentration of about 10{sup 15}/cm{sup 3}). Anodic etching in 5 wt % hydrofluoric acid produces crystallographic etch pits which correlate with both structural and impurity defects. Etch pit densities also correlate well with reported values of defect densities calculated from gate oxide breakdown. We show that the method is particularly suited to defect delineation in thin-film silicon-on-insulator (SOI) wafers. The technique is superior to chemical decoration etches and to transmission electron microscopy for defect delineation in thin-film SOI wafers since it does not etch bulk silicon and it has a detection limit much lower than 10{sup 4}--10{sup 5} defects/cm{sup 2}. We used the procedure to demonstrate how defect levels are strongly affected by the process parameters used to synthesize Zone Melt Recrystallization (ZMR) and Separation by IMplanted OXygen (SIMOX) wafers. 10 refs., 6 figs.
- Research Organization:
- Sandia National Labs., Albuquerque, NM (USA)
- Sponsoring Organization:
- DOE/DP
- DOE Contract Number:
- AC04-76DP00789
- OSTI ID:
- 7008008
- Report Number(s):
- SAND-89-2696C; CONF-900598--1; ON: DE90006020
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
360602* -- Other Materials-- Structure & Phase Studies
42 ENGINEERING
426000 -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
CONTAMINATION
DEFECTS
ELECTRONIC CIRCUITS
ELEMENTS
ETCHING
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
SEMIMETALS
SILICON
SPECTROSCOPY
SUBSTRATES
SURFACE FINISHING