CMOS IC fault models, physical defect coverage, and IDDQ testing [Book Chapter]

Fritzemeier, Robert R.; Hawkins, Charles F.; Soden, Jerry M.

doi:10.1109/cicc.1991.164091

CMOS IC fault models, physical defect coverage, and I_DDQ testing [Book Chapter]

Conference · Sun May 12 00:00:00 EDT 1991 · Proceedings of the IEEE 1991 Custom Integrated Circuits Conference

DOI:https://doi.org/10.1109/cicc.1991.164091· OSTI ID:6018784

Fritzemeier, Robert R. ^[1]; Hawkins, Charles F. ^[2]; Soden, Jerry M. ^[1]

Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)
Univ. of New Mexico, Albuquerque, NM (United States)

The development of the stuck-at fault (SAF) model is reviewed with emphasis on its relationship to CMOS integrated circuit (IC) technologies. The ability of the SAF model to represent common physical defects in CMOS ICs is evaluated. A test strategy for defect detection, which includes I/sub DDQ/ testing is presented.

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Research Organization:: Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)

Sponsoring Organization:: USDOE

DOE Contract Number:: AC04-76DP00789

OSTI ID:: 6018784

Report Number(s):: SAND--90-2900C; CONF-910504--1; ON: DE91010579; ISBN: 0-7803-0015-7

Journal Information:: Proceedings of the IEEE 1991 Custom Integrated Circuits Conference, Journal Name: Proceedings of the IEEE 1991 Custom Integrated Circuits Conference

Publisher:: IEEE

Country of Publication:: United States

Language:: English

References (17)

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Related Subjects

42 ENGINEERING
426000* -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
CONTROL
CURRENTS
DEFECTS
ELECTRIC CURRENTS
ELECTRONIC CIRCUITS
ELECTRONIC EQUIPMENT
EQUIPMENT
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
MOS TRANSISTORS
POWER SUPPLIES
QUALITY CONTROL
SEMICONDUCTOR DEVICES
TESTING
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CMOS IC fault models, physical defect coverage, and IDDQ testing [Book Chapter]

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References (17)

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CMOS IC fault models, physical defect coverage, and I_DDQ testing [Book Chapter]