Increased stuck-at fault coverage with reduced I sub DDQ test sets

Conference · Sun Dec 31 23:00:00 EST 1989

DOI:https://doi.org/10.1109/TEST.1990.114051· OSTI ID:7202990

Fritzemeier, R R; Soden, J M; Treece, R K ^[1]; Hawkins, C F ^[2]

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1. Sandia National Labs., Albuquerque, NM (USA)
2. New Mexico Univ., Albuquerque, NM (USA). Dept. of Electrical and Computer Engineering

Simplified ATPG and fault simulation algorithms, reduced test set sizes, and increased fault coverage are achieved with I {sub DDQ} testing for stuck-at faults. In addition, I {sub DDQ} testing will detect logically redundant and multiple stuck-at faults, and improve the detection of non-stuck-at fault defects. 17 refs., 6 figs., 6 tabs.

• Research Organization: New Mexico Univ., Albuquerque, NM (USA). Dept. of Electrical and Computer Engineering
• Sponsoring Organization: DOE/DP
• DOE Contract Number: AC04-76DP00789
• OSTI ID: 7202990
• Report Number(s): SAND-90-0608C; CONF-9005158--1; ON: DE90009509
• Country of Publication: United States
• Language: English

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42 ENGINEERING
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Electron Devices & Circuits-- (1990-)
99 GENERAL AND MISCELLANEOUS
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ALGORITHMS
AUTOMATION
COMPARATIVE EVALUATIONS
DEFECTS
ECONOMICS
ELECTRONIC CIRCUITS
FUNCTIONS
INTEGRATED CIRCUITS
MANUFACTURING
MATERIALS
MATHEMATICAL LOGIC
MEASURING METHODS
MICROELECTRONIC CIRCUITS
OPERATION
RESPONSE FUNCTIONS
SEMICONDUCTOR MATERIALS
SIMULATION
TESTING