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U.S. Department of Energy
Office of Scientific and Technical Information

Phase 2 of the automated array assembly task of the low-cost silicon solar array project. Technical quarterly report No. 4, April 1-June 30, 1979

Technical Report ·
DOI:https://doi.org/10.2172/5629155· OSTI ID:5629155
During this period, all tasks progressed according to scheduled plans. This report highlights the process verification efforts, ion implantation investigations, plasma etching, and cost factors in the metallization processes. Completed modules were delivered to JPL to demonstrate the process sequence. A surface film has been observed on ion implanted wafers which was tentatively been associated with break-down of the vacuum pump oil during implantation. A baseline process for plasma patterning of silicon nitride on a silicon substrate has been specified. In addition, copper has been shown to have strong cost advantages over other metals for a conductor layer; and nickel has been identified as a desirable barrier between copper and silicon.
Research Organization:
Motorola, Inc., Phoenix, AZ (USA). Semiconductor Group
DOE Contract Number:
NAS-7-100-954847
OSTI ID:
5629155
Report Number(s):
DOE/JPL/954847-79/5
Country of Publication:
United States
Language:
English