Schottky barrier MOSFET systems and fabrication thereof
- 10328 Pinehurst Ave., Omaha, NE 68124
(MOS) device systems-utilizing Schottky barrier source and drain to channel region junctions are disclosed. Experimentally derived results which demonstrate operation of fabricated N-channel and P-channel Schottky barrier (MOSFET) devices, and of fabricated single devices with operational characteristics similar to (CMOS) and to a non-latching (SRC) are reported. Use of essentially non-rectifying Schottky barriers in (MOS) structures involving highly doped and the like and intrinsic semiconductor to allow non-rectifying interconnection of, and electrical accessing of device regions is also disclosed. Insulator effected low leakage current device geometries and fabrication procedures therefore are taught. Selective electrical interconnection of drain to drain, source to drain, or source to source, of N-channel and/or P-channel Schottky barrier (MOSFET) devices formed on P-type, N-type and Intrinsic semiconductor allows realization of Schottky Barrier (CMOS), (MOSFET) with (MOSFET) load, balanced differential (MOSFET) device systems and inverting and non-inverting single devices with operating characteristics similar to (CMOS), which devices can be utilized in modulation, as well as in voltage controled switching and effecting a direction of rectification.
- Research Organization:
- James D Welch
- DOE Contract Number:
- FG47-93R701314
- Assignee:
- Welch, James D. (10328 Pinehurst Ave., Omaha, NE 68124)
- Patent Number(s):
- US 5663584
- OSTI ID:
- 871132
- Country of Publication:
- United States
- Language:
- English
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journal | December 1976 |
Metallurgical and electrical properties of chromium silicon interfaces
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journal | January 1980 |
Compound formation between amorphous silicon and chromium
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journal | December 1980 |
SB-IGFET: An insulated-gate field-effect transistor using Schottky barrier contacts for source and drain
|
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