Development of pixel detectors for SSC vertex tracking
- Hughes Aircraft Co., El Segundo, CA (USA). Electro-Optical and Data Systems Group
- California Univ., Berkeley, CA (USA). Space Sciences Lab.
A description of hybrid PIN diode arrays and a readout architecture for their use as a vertex detector in the SSC environment is presented. Test results obtained with arrays having 256 {times} 256 pixels, each 30 {mu}m square, are also presented. The development of a custom readout for the SSC will be discussed, which supports a mechanism for time stamping hit pixels, storing their xy coordinates, and storing the analog information within the pixel. The peripheral logic located on the array, permits the selection of those pixels containing interesting data and their coordinates to be selectively read out. This same logic also resolves ambiguous pixel ghost locations and controls the pixel neighbor read out necessary to achieve high spatial resolution. The thermal design of the vertex tracker and the proposed signal processing architecture will also be discussed. 5 refs., 13 figs., 3 tabs.
- Research Organization:
- Stanford Linear Accelerator Center, Menlo Park, CA (USA)
- Sponsoring Organization:
- USDOE; USDOE, Washington, DC (USA)
- DOE Contract Number:
- AC03-76SF00515
- OSTI ID:
- 5632325
- Report Number(s):
- SLAC-PUB-5518; CONF-910340-33; ON: DE91013276
- Resource Relation:
- Conference: 3. annual international industrial symposium on the super collider (IISSC), Atlanta, GA (USA), 13-15 Mar 1991
- Country of Publication:
- United States
- Language:
- English
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