Development of a customized SSC pixel detector readout for vertex tracking

Conference · Mon Oct 01 00:00:00 EDT 1990

OSTI ID:6373450

Barkan, O; Atlas, E L; Marking, W L; Worley, S; Yacoub, G Y ^[1]; Kramer, G ^[2]; Arens, J F; Jernigan, J G ^[3]; Shapiro, S L ^[4]; Nygren, D; Spieler, H; Wright, M ^[5]

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1. Hughes Aircraft Co., Carlsbad, CA (USA)
2. Hughes Aircraft Co., El Segundo, CA (USA)
3. California Univ., Berkeley, CA (USA). Space Sciences Lab.
4. Stanford Linear Accelerator Center, Menlo Park, CA (USA)
5. Lawrence Berkeley Lab., CA (USA)

We describe the readout architecture and progress to date in the development of hybrid PIN diode arrays for use as vertex detectors in the SSC environment. The architecture supports a self-timed mechanism for time stamping hit pixels, storing their xy coordinates and later selectively reading out only those pixels containing interesting data along with their coordinates. The peripheral logic resolves ambiguous pixel ghost locations and controls pixel neighbor readout to achieve high spatial resolution. A test lot containing 64 {times} 32 pixel arrays has been processed and is currently being tested. Each pixel contains 23 transistors and six capacitors consuming an area of 50 {mu}m by 150 {mu}m and dissipating about 20{mu}W of power. 6 refs., 2 figs.

• Research Organization: Stanford Linear Accelerator Center, Menlo Park, CA (USA)
• Sponsoring Organization: DOE/ER
• DOE Contract Number: AC03-76SF00515; AC03-76SF00098
• OSTI ID: 6373450
• Report Number(s): SLAC-PUB-5358; CONF-9010212-22; LBL-29792; ON: DE91004684; TRN: 90-037687
• Resource Relation: Conference: Symposium on detector research and development for the Superconducting Super Collider, Fort Worth, TX (USA), 15-18 Oct 1990
• Country of Publication: United States
• Language: English

Related Subjects

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
43 PARTICLE ACCELERATORS
SI SEMICONDUCTOR DETECTORS
COMPUTER ARCHITECTURE
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ELECTRONIC CIRCUITS
MEASURING INSTRUMENTS
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