Design of a pixel cell optimized for a data push architecture readout

Technical Report · Tue Dec 01 00:00:00 EST 1992

DOI:https://doi.org/10.2172/6661055· OSTI ID:6661055

Atlas, E L ^[1]; Shapiro, S; Cords, D ^[2]

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1. Adept IC Design, Oceanside, CA (United States)
2. Stanford Linear Accelerator Center, Menlo Park, CA (United States)

A pixel cell has been designed which has been optimized for a data push architecture readout. It retains the features of preceding designs which allow time stamping, analog signal processing, XY address recording, ghost elimination and sparse data transmission. It eliminates a number of problems inherent in previous designs by use of sampled data techniques, destructive readout sampled data techniques, and current mode output drivers. This document examines the motivation for this new pixel and covers the theory of operation of the various blocks. A discussion of the tradeoffs affecting speed, power, device size, and radiation stability is included as well.

• Research Organization: SLAC National Accelerator Lab., Menlo Park, CA (United States)
• Sponsoring Organization: USDOE; USDOE, Washington, DC (United States)
• DOE Contract Number: AC03-76SF00515
• OSTI ID: 6661055
• Report Number(s): SLAC-TN-92-2; ON: DE93011016
• Country of Publication: United States
• Language: English

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46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
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DATA PROCESSING
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ELECTRONIC EQUIPMENT
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PHYSICAL RADIATION EFFECTS
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