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Title: Apparatus and method for implementing power saving techniques when processing floating point values

Patent ·
OSTI ID:1397247
;

An apparatus and method are described for reducing power when reading and writing graphics data. For example, one embodiment of an apparatus comprises: a graphics processor unit (GPU) to process graphics data including floating point data; a set of registers, at least one of the registers of the set partitioned to store the floating point data; and encode/decode logic to reduce a number of binary 1 values being read from the at least one register by causing a specified set of bit positions within the floating point data to be read out as 0s rather than 1s.

Research Organization:
Intel Corporation, Santa Clara, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
B600738
Assignee:
Intel Corporation
Patent Number(s):
9,779,465
Application Number:
14/581,600
OSTI ID:
1397247
Resource Relation:
Patent File Date: 2014 Dec 23
Country of Publication:
United States
Language:
English

References (10)

Method and apparatus for low power memory patent August 2003
Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointer patent October 2003
Apparatus and method for reduction of processor power consumption patent April 2008
Power saving in a floating point unit using a multiplier and aligner bypass patent-application September 2004
Zero Indication Forwarding for Floating Point Unit Power Reduction patent-application November 2012
Approach to power reduction in floating-point operations patent-application May 2014
Reducing the power consumption of memory devices patent-application June 2014
Adaptive Video Reference Frame Compression with Control Elements patent-application December 2014
Apparatus and method for improving data storage by data inversion patent-application July 2015
Encoding for partitioned data bus patent-application August 2015

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97 MATHEMATICS AND COMPUTING