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Low energy consumption mantissa multiplication for floating point multiply-add operations

Patent ·
OSTI ID:1576396
A floating point multiply-add unit having inputs coupled to receive a floating point multiplier data element, a floating point multiplicand data element, and a floating point addend data element. The multiply-add unit including a mantissa multiplier to multiply a mantissa of the multiplier data element and a mantissa of the multiplicand data element to calculate a mantissa product. The mantissa multiplier including a most significant bit portion to calculate most significant bits of the mantissa product, and a least significant bit portion to calculate least significant bits of the mantissa product. The mantissa multiplier has a plurality of different possible sizes of the least significant bit portion. Energy consumption reduction logic to selectively reduce energy consumption of the least significant bit portion, but not the most significant bit portion, to cause the least significant bit portion to not calculate the least significant bits of the mantissa product.
Research Organization:
Intel Corp., Santa Clara, CA (United States)
Sponsoring Organization:
USDOE
Assignee:
Intel Corporation (Santa Clara, CA)
Patent Number(s):
10,402,168
Application Number:
15/283,295
OSTI ID:
1576396
Country of Publication:
United States
Language:
English

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