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Title: Generating and executing programs for a floating point single instruction multiple data instruction set architecture

Abstract

Mechanisms for generating and executing programs for a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA) are provided. A computer program product comprising a computer recordable medium having a computer readable program recorded thereon is provided. The computer readable program, when executed on a computing device, causes the computing device to receive one or more instructions and execute the one or more instructions using logic in an execution unit of the computing device. The logic implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA), based on data stored in a vector register file of the computing device. The vector register file is configured to store both scalar and floating point values as vectors having a plurality of vector elements.

Inventors:
Publication Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1083443
Patent Number(s):
8,423,983
Application Number:
12/250,581
Assignee:
International Business Machines Corporation (Armonk, NY)
DOE Contract Number:  
B554331
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Gschwind, Michael K. Generating and executing programs for a floating point single instruction multiple data instruction set architecture. United States: N. p., 2013. Web.
Gschwind, Michael K. Generating and executing programs for a floating point single instruction multiple data instruction set architecture. United States.
Gschwind, Michael K. Tue . "Generating and executing programs for a floating point single instruction multiple data instruction set architecture". United States. https://www.osti.gov/servlets/purl/1083443.
@article{osti_1083443,
title = {Generating and executing programs for a floating point single instruction multiple data instruction set architecture},
author = {Gschwind, Michael K},
abstractNote = {Mechanisms for generating and executing programs for a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA) are provided. A computer program product comprising a computer recordable medium having a computer readable program recorded thereon is provided. The computer readable program, when executed on a computing device, causes the computing device to receive one or more instructions and execute the one or more instructions using logic in an execution unit of the computing device. The logic implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA), based on data stored in a vector register file of the computing device. The vector register file is configured to store both scalar and floating point values as vectors having a plurality of vector elements.},
doi = {},
url = {https://www.osti.gov/biblio/1083443}, journal = {},
number = ,
volume = ,
place = {United States},
year = {2013},
month = {4}
}

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