Skip to main content
OSTI.GOVU.S. Department of Energy Office of Scientific and Technical Information
U.S. Department of Energy
Office of Scientific and Technical Information
 

Generating and executing programs for a floating point single instruction multiple data instruction set architecture

Patent ·
OSTI ID:1083443
Mechanisms for generating and executing programs for a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA) are provided. A computer program product comprising a computer recordable medium having a computer readable program recorded thereon is provided. The computer readable program, when executed on a computing device, causes the computing device to receive one or more instructions and execute the one or more instructions using logic in an execution unit of the computing device. The logic implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA), based on data stored in a vector register file of the computing device. The vector register file is configured to store both scalar and floating point values as vectors having a plurality of vector elements.
Research Organization:
International Business Machines Corporation (Armonk, NY)
Sponsoring Organization:
USDOE
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Number(s):
8,423,983
Application Number:
12/250,581
OSTI ID:
1083443
Country of Publication:
United States
Language:
English

References (15)

Logical inference techniques for loop parallelization journal August 2012
Optimizing Compiler for the CELL Processor
  • Eichenberger, A. E.; O'Brien, K.; O'Brien, K.
  • PACT 2005. 14th International Conference on Parallel Architectures and Compilation Techniques, 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05) https://doi.org/10.1109/PACT.2005.33
conference January 2005
Compiler analysis for cache coherence: interprocedural array data-flow analysis and its impact on cache performance journal January 2000
Chip multiprocessing and the cell broadband engine conference January 2006
DFG Program journal December 1999
A high-performance SIMD floating point unit for BlueGene/L: architecture, compilation, and algorithm design conference January 2004
Automatic Intra-Register Vectorization for the Intel® Architecture journal January 2002
Using advanced compiler technology to exploit the performance of the Cell Broadband Engine™ architecture journal January 2006
Vectorization for SIMD architectures with alignment constraints
  • Eichenberger, Alexandre E.; Wu, Peng; O'Brien, Kevin
  • Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation - PLDI '04 https://doi.org/10.1145/996841.996853
conference January 2004
An Open Source Environment for Cell Broadband Engine System Software journal June 2007
The Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a Chip Multiprocessor journal April 2007
Synergistic Processing in Cell's Multicore Architecture journal March 2006
SIMD Vectorization of Straight Line FFT Code book January 2003
An integrated simdization framework using virtual vectors conference January 2005
IBM PowerPC 440 FPU with complex-arithmetic extensions journal March 2005

Similar Records

Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations
Patent · Mon Feb 28 23:00:00 EST 2011 · OSTI ID:1018063
Heterogeneous graphics processing unit for scheduling thread groups for execution on variable width SIMD units
Patent · Tue Jul 14 00:00:00 EDT 2020 · OSTI ID:1735025
Index Sets and Vectorization
Conference · Tue Mar 27 00:00:00 EDT 2012 · OSTI ID:1046799

Related Subjects

97 MATHEMATICS AND COMPUTING