Generating and executing programs for a floating point single instruction multiple data instruction set architecture

Gschwind, Michael K

Generating and executing programs for a floating point single instruction multiple data instruction set architecture

Patent · Tue Apr 16 00:00:00 EDT 2013

OSTI ID:1083443

Gschwind, Michael K

Mechanisms for generating and executing programs for a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA) are provided. A computer program product comprising a computer recordable medium having a computer readable program recorded thereon is provided. The computer readable program, when executed on a computing device, causes the computing device to receive one or more instructions and execute the one or more instructions using logic in an execution unit of the computing device. The logic implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA), based on data stored in a vector register file of the computing device. The vector register file is configured to store both scalar and floating point values as vectors having a plurality of vector elements.

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Research Organization:: International Business Machines Corporation (Armonk, NY)

Sponsoring Organization:: USDOE

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Number(s):: 8,423,983

Application Number:: 12/250,581

OSTI ID:: 1083443

Country of Publication:: United States

Language:: English

References (15)

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