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Title: Heterogeneous graphics processing unit for scheduling thread groups for execution on variable width SIMD units

Abstract

A compute unit configured to execute multiple threads in parallel is presented. The compute unit includes one or more single instruction multiple data (SIMD) units and a fetch and decode logic. The SIMD units have differing numbers of arithmetic logic units (ALUs), such that each SIMD unit can execute a different number of threads. The fetch and decode logic is in communication with each of the SIMD units, and is configured to assign the threads to the SIMD units for execution based on such differing numbers of ALUs.

Inventors:
; ; ; ;
Publication Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1735025
Patent Number(s):
10,713,059
Application Number:
14/490,213
Assignee:
Advanced Micro Devices, Inc. (Sunnyvale, CA)
DOE Contract Number:  
AC52-07NA27344; B600716
Resource Type:
Patent
Resource Relation:
Patent File Date: 09/18/2014
Country of Publication:
United States
Language:
English

Citation Formats

Greathouse, Joseph L., Meswani, Mitesh R., Puthoor, Sooraj, Yudanov, Dmitri, and O'Connor, James M. Heterogeneous graphics processing unit for scheduling thread groups for execution on variable width SIMD units. United States: N. p., 2020. Web.
Greathouse, Joseph L., Meswani, Mitesh R., Puthoor, Sooraj, Yudanov, Dmitri, & O'Connor, James M. Heterogeneous graphics processing unit for scheduling thread groups for execution on variable width SIMD units. United States.
Greathouse, Joseph L., Meswani, Mitesh R., Puthoor, Sooraj, Yudanov, Dmitri, and O'Connor, James M. 2020. "Heterogeneous graphics processing unit for scheduling thread groups for execution on variable width SIMD units". United States. https://www.osti.gov/servlets/purl/1735025.
@article{osti_1735025,
title = {Heterogeneous graphics processing unit for scheduling thread groups for execution on variable width SIMD units},
author = {Greathouse, Joseph L. and Meswani, Mitesh R. and Puthoor, Sooraj and Yudanov, Dmitri and O'Connor, James M.},
abstractNote = {A compute unit configured to execute multiple threads in parallel is presented. The compute unit includes one or more single instruction multiple data (SIMD) units and a fetch and decode logic. The SIMD units have differing numbers of arithmetic logic units (ALUs), such that each SIMD unit can execute a different number of threads. The fetch and decode logic is in communication with each of the SIMD units, and is configured to assign the threads to the SIMD units for execution based on such differing numbers of ALUs.},
doi = {},
url = {https://www.osti.gov/biblio/1735025}, journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {7}
}