Heterogeneous graphics processing unit for scheduling thread groups for execution on variable width SIMD units
Patent
·
OSTI ID:1735025
A compute unit configured to execute multiple threads in parallel is presented. The compute unit includes one or more single instruction multiple data (SIMD) units and a fetch and decode logic. The SIMD units have differing numbers of arithmetic logic units (ALUs), such that each SIMD unit can execute a different number of threads. The fetch and decode logic is in communication with each of the SIMD units, and is configured to assign the threads to the SIMD units for execution based on such differing numbers of ALUs.
- Research Organization:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC52-07NA27344
- Assignee:
- Advanced Micro Devices, Inc. (Sunnyvale, CA)
- Patent Number(s):
- 10,713,059
- Application Number:
- 14/490,213
- OSTI ID:
- 1735025
- Country of Publication:
- United States
- Language:
- English
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