Method and apparatus for asynchronous scheduling
A method and apparatus of asynchronous scheduling in a graphics device includes sending one or more instructions from an instruction scheduler to one or more instruction first-in/first-out (FIFO) devices. An instruction in the one or more FIFO devices is selected for execution by a single-instruction/multiple-data (SIMD) pipeline unit. It is determined whether all operands for the selected instruction are available for execution of the instruction, and if all the operands are available, the selected instruction is executed on the SIMD pipeline unit. The self-timed arithmetic pipeline unit (SIMD pipeline unit) is effectively encapsulated in a synchronous, (e.g., clocked by global clock), scheduler and register file environment.
- Research Organization:
- Advanced Micro Devices, Inc., Sunnyvale, CA (United States); ATI Technologies ULC, Markham, CA (United States); Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC52-07NA27344
- Assignee:
- ATI Technologies UL (Markham, CA); Advanced Micro Devices, Inc. (Sunnyvale, CA)
- Patent Number(s):
- 11,023,242
- Application Number:
- 15/417,555
- OSTI ID:
- 1824026
- Country of Publication:
- United States
- Language:
- English
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