Code generation and instruction scheduling for pipelined SISD machines

Thesis/Dissertation · Thu Jan 01 04:00:00 EST 1987

OSTI ID:6565896

Bird, P H

Some very sophisticated pipelines are designed to perform dynamic scheduling. While execution-time instruction scheduling and conflict detection provides for a very accurate determination of resource clashes, the hardware to do this is costly and complex. For programs running on scalar, sequential computers, instruction scheduling can be done once, when the user's program is compiled, thereby eliminating the need for any runtime checks. Static scheduling of instruction is difficult. The author shows that even for programs comprised of a single arithmetic expression having no shared operands (which could be represented by a tree-like graph), finding an optimal schedule for execution on a sequential machine whose architecture is pipelined can be considered computationally intractable and probably requires an exponential time algorithm to compute. For realistic programs, however, he shows that the problem is similar to scheduling tasks on a multiprocessor system under constraints that enable an optimal schedule to be quickly computed. He shows how to incorporate instruction scheduling (and the required register allocation) into the code-generation phase of program compilation. The implementation demonstrates that scheduling instruction to increase pipeline throughput can be routinely incorporated into optimizing compilers.

• Research Organization: Michigan Univ., Ann Arbor (USA)
• OSTI ID: 6565896
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210 -- Supercomputers-- (1987-1989)
990300* -- Information Handling
ALGORITHMS
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
COMPUTER NETWORKS
CONSTRAINTS
DATA PROCESSING
DISTRIBUTED DATA PROCESSING
MATHEMATICAL LOGIC
OPTIMIZATION
PROCESSING
TASK SCHEDULING