Retargetable instruction scheduling for pipelined processors

Thesis/Dissertation · Tue Jan 01 04:00:00 EST 1991

OSTI ID:5431106

Bradlee, D G

Retargetable code generators for complex instruction-set computers (CISCs) have focused on sophisticated pattern-matching code selection, because CISCs provide many machine instruction sequence choices. Recent pipelined processors, known as reduced-instruction set computers (RISCs), provide fewer instruction-sequence choices, but expose pipeline and functional unit costs to the compiler. This dissertation comprises three components. The first component discusses the Marion retargetable code generator system, which includes a machine description language that contains instruction-scheduling requirements, along with other code-generation information. Using Marion, code generators were constructed for the MIPS R2000, Motorola 88000, Intel i860. The second component compares three code-generation strategies for handling the interaction between instruction scheduling and register allocation. The third component investigates the interaction between code-generation strategies and architectural features, including register set size and structure, and operation and load latencies.

• Research Organization: Washington Univ., Seattle, WA (United States)
• OSTI ID: 5431106
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
COMPUTER CODES
DATA PROCESSING
OPERATION
PROCESSING
PROGRAMMING
PROGRAMMING LANGUAGES
TASK SCHEDULING
VECTOR PROCESSING