Lisp on a reduced-instruction-set processor: Characterization and optimization

Journal Article · Fri Jul 01 04:00:00 EDT 1988 · Computer; (United States)

DOI:https://doi.org/10.1109/2.67· OSTI ID:7177768

Steenkiste, P; Hennessy, J

When designing a machine for a high-level language (HLL), the authors must decide how to divide the required functionality between hardware and software. The two current approaches use HLL-specific machines and reduced-instruction-set computing (RISC). In determining which approach to use to implement Lisp, the authors faced several questions. To answer these questions, their strategy was to first collect data on what Lisp operations are time-critical using a set of 10 programs. The authors then used the same set of programs to evaluate and compare software optimizations and hardware support for these important operations. They used MIPS-X as a typical example of a RISC processor, but their approach and most of their results are applicable to other architectures and languages. At the end of the article the authors compare the performance of MIPS-X for Lisp with other systems using the Gabriel benchmark set.

• Research Organization: Stanford Univ. (US)
• OSTI ID: 7177768
• Journal Information: Computer; (United States), Journal Name: Computer; (United States) Vol. 21:7; ISSN CPTRB
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
COMPARATIVE EVALUATIONS
COMPUTER ARCHITECTURE
ELECTRONIC CIRCUITS
INTEGRATED CIRCUITS
LISP
MICROELECTRONIC CIRCUITS
OPTIMIZATION
PROGRAMMING LANGUAGES