Apparatus and method for synchronization of a coprocessor unit in a pipelined central processing unit
This patent describes a pipelined central processing unit capable of executing a first set of instructions and special instructions. The central processing unit comprising: an instruction cache memory unit for storing instructions to be executed; an instruction register for processing an executing instruction from the instruction cache memory unit; an operand cache memory unit for storing operands to be processed; at least one operand register for storing an operand to be processed in response to the executing instruction; an arithmetic logic unit coupled to the instruction register and to the operand register for performing an operation on the operand to be processed in a manner determined by the executing instruction when the executing instruction is selected from the first set of instructions; storage means coupled to the coprocessor unit for storing a resulting operand provided by the coprocessor unit; first means coupled to the storage means and responsive to a presence of the resulting operand stored in the storage means for applying a first signal to the instruction register; and second means coupled to the instruction register and responsive to the first signal for preventing processing of an executing instruction when the executing instruction is a special instruction until the first signal is present.
- Assignee:
- Digital Equipment Corp., Maynard, MA (USA)
- Patent Number(s):
- A; US 4943915
- Application Number:
- PPN: US s 7-101984
- OSTI ID:
- 6473540
- Country of Publication:
- United States
- Language:
- English
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