Apparatus and method for improving cache access throughput in pipelined processors
Patent
·
OSTI ID:6937986
This patent describes in a data processing system including an instruction unit, a main store storing system data, and a storage unit having a high speed cache storing a subset of the data retrieved from the main store, an apparatus for improving storage unit utilization during interlocks. It comprises: means, coupled to the first register, for generating a control signal during one cycle of an interlock if the interlocked instruction may require cache access; and means, responsive to the control signal and coupled to the selector control logic, for changing the assigned priority of the first register.
- Assignee:
- Amdahl Corp., Sunnyvale, CA
- Patent Number(s):
- A; US 4888689
- Application Number:
- PPN: US 6-920805A
- OSTI ID:
- 6937986
- Country of Publication:
- United States
- Language:
- English
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