Method for implementing synchronous pipeline exception recovery
This patent describes a processor. It comprises: an execution unit for accessing operands from local registers, performing operations on the operands, and for storing results of the operations; a memory interface unit, including a memory-request stage for receiving memory address from the execution unit and a memory-access stage for evaluating the memory address to determine if it is available for access and for accessing a memory if the address is available or for issuing an exception control signal if the memory address is not available for access; pipelining means for applying sets of control bits to each of the stages of the execution unit and to each of the memory-request and memory-access stage of the memory interface unit in successive ones of machine cycles of the processor; and latch means for holding a set of the control bits when the exception control signal is issued in a given one of the machine cycles, and for thereafter re-applying the set of control bits to the memory-access stage after the given machine cycle.
- Assignee:
- Digital Equipment Corp., Maynard, MA
- Patent Number(s):
- US 4875160
- Application Number:
- PPN: US 7-221934A
- OSTI ID:
- 6996341
- Country of Publication:
- United States
- Language:
- English
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