Bit-serial SIMD on the CM-2 and the Cray-2
- Supercomputing Research Center, Bowie, MD (US)
The term Single Instruction, Multiple Data or SIMD has been used to categorize a particular architecture in which each instruction is broadcast to a large number of processors. Each processor then executes that instruction using data local to itself. However, the SIMD concept can also be viewed as a model of computation. In this paper, two different machine architectures for supporting a SIMD programming model with one-bit granularity are investigated. One machine, the CM-2, is a bit-level parallel processor. The other machine, the Cray-2, is a vector processor with 64-bit- wide functional units that is programmed to support a bit- serial SIMD programming model. Benchmarking studies are used to compare its ability to support bit-serial SIMD to that of the CM-2.
- OSTI ID:
- 5001363
- Journal Information:
- Journal of Parallel and Distributed Computing; (United States), Journal Name: Journal of Parallel and Distributed Computing; (United States) Vol. 11:2; ISSN 0743-7315; ISSN JPDCE
- Country of Publication:
- United States
- Language:
- English
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