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Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations

Patent ·
OSTI ID:1018063
 [1]
  1. Chappaqua, NY
+ Show Author Affiliations

Mechanisms for implementing a floating point only single instruction multiple data instruction set architecture are provided. A processor is provided that comprises an issue unit, an execution unit coupled to the issue unit, and a vector register file coupled to the execution unit. The execution unit has logic that implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA). The floating point vector registers of the vector register file store both scalar and floating point values as vectors having a plurality of vector elements. The processor may be part of a data processing system.

Research Organization:
International Business Machines Corporation, Armonk, NY (United States)
Sponsoring Organization:
USDOE
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Number(s):
7,900,025
Application Number:
12/250,575
OSTI ID:
1018063
Country of Publication:
United States
Language:
English

References (8)

Optimizing Compiler for the CELL Processor
  • Eichenberger, A. E.; O'Brien, K.; O'Brien, K.
  • PACT 2005. 14th International Conference on Parallel Architectures and Compilation Techniques, 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05) https://doi.org/10.1109/PACT.2005.33
conference January 2005
DFG Program journal December 1999
Automatic Intra-Register Vectorization for the Intel® Architecture journal January 2002
Using advanced compiler technology to exploit the performance of the Cell Broadband Engine™ architecture journal January 2006
Vectorization for SIMD architectures with alignment constraints
  • Eichenberger, Alexandre E.; Wu, Peng; O'Brien, Kevin
  • Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation - PLDI '04 https://doi.org/10.1145/996841.996853
conference January 2004
Synergistic Processing in Cell's Multicore Architecture journal March 2006
An integrated simdization framework using virtual vectors conference January 2005
IBM PowerPC 440 FPU with complex-arithmetic extensions journal March 2005

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Related Subjects

97 MATHEMATICS AND COMPUTING