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Title: Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations

Abstract

Mechanisms for implementing a floating point only single instruction multiple data instruction set architecture are provided. A processor is provided that comprises an issue unit, an execution unit coupled to the issue unit, and a vector register file coupled to the execution unit. The execution unit has logic that implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA). The floating point vector registers of the vector register file store both scalar and floating point values as vectors having a plurality of vector elements. The processor may be part of a data processing system.

Inventors:
 [1]
  1. Chappaqua, NY
Publication Date:
Research Org.:
International Business Machines Corporation (Armonk, NY)
Sponsoring Org.:
USDOE
OSTI Identifier:
1018063
Patent Number(s):
7,900,025
Application Number:
12/250,575
Assignee:
International Business Machines Corporation (Armonk, NY) OSTI
DOE Contract Number:
B554331
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Gschwind, Michael K. Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations. United States: N. p., 2011. Web.
Gschwind, Michael K. Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations. United States.
Gschwind, Michael K. Tue . "Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations". United States. doi:. https://www.osti.gov/servlets/purl/1018063.
@article{osti_1018063,
title = {Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations},
author = {Gschwind, Michael K},
abstractNote = {Mechanisms for implementing a floating point only single instruction multiple data instruction set architecture are provided. A processor is provided that comprises an issue unit, an execution unit coupled to the issue unit, and a vector register file coupled to the execution unit. The execution unit has logic that implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA). The floating point vector registers of the vector register file store both scalar and floating point values as vectors having a plurality of vector elements. The processor may be part of a data processing system.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Mar 01 00:00:00 EST 2011},
month = {Tue Mar 01 00:00:00 EST 2011}
}

Patent:

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