Software implementation of floating-Point arithmetic on a reduced-Instruction-set processor

Journal Article · Thu Oct 31 23:00:00 EST 1985 · J. Parallel Distrib. Comput.; (United States)

DOI:https://doi.org/10.1016/0743-7315(85)90020-6· OSTI ID:6594544

Gross, T

Current single chip implementations of reduced-instruction-set processors do not support hardware floating-point operations. Instead, floating-point operations have to be provided either by a coprocessor or by software. This paper discusses issues arising from a software implementation of floating-point arithmetic for the MIPS processor, an experimental VLSI architecture. Measurements indicate that an acceptable level of performance is achieved, but this approach is no substitute for a hardware accelerator if higher-precision results are required. This paper includes instruction profiles for the basic floating-point operations and evaluates the usefulness of some aspects of the instruction set.

• Research Organization: Dept. of Computer Science, Carnegie-Mellon Univ., Pittsburgh, PA 15213
• OSTI ID: 6594544
• Journal Information: J. Parallel Distrib. Comput.; (United States), Journal Name: J. Parallel Distrib. Comput.; (United States) Vol. 2:4; ISSN JPDCE
• Country of Publication: United States
• Language: English

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